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41C16256 데이터시트 PDF




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41C16256 데이터시트, 핀배열, 회로
www.DaIStaS4he1eCt4U1.c6om256
IS41LV16256
256K x 16 (4-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
FEATURES
• Extended Data-Out (EDO) Page Mode access cycle
• TTL compatible inputs and outputs; tristate I/O
• Refresh Interval: 512 cycles /8 ms
• Refresh Mode: RAS-Only, CAS-before-RAS (CBR),
Hidden
• Single power supply:
5V ± 10% (IS41C16256)
3.3V ± 10% (IS41LV16256)
• Byte Write and Byte Read operation via two CAS
• Industrial Temperature Range -40oC to 85oC
DESCRIPTION
The ICSI IS41C16256 and IS41LV16256 is a 262,144 x 16-
bit high-performance CMOS Dynamic Random Access Memo-
ries. The IS41C16256 offer an accelerated cycle access
called EDO Page Mode. EDO Page Mode allows 512 random
accesses within a single row with access cycle time as short
as 10 ns per 16-bit word. The Byte Write control, of upper and
lower byte, makes the IS41C16256 ideal for use in
16-, 32-bit wide data bus systems.
These features make the IS41C16256and IS41LV16256 ideally
suited for high-bandwidth graphics, digital signal processing,
high-performance computing systems, and peripheral
applications.
KEY TIMING PARAMETERS
Parameter
Max. RAS Access Time (tRAC)
Max. CAS Access Time (tCAC)
Max. Column Address Access Time (tAA)
Min. EDO Page Mode Cycle Time (tPC)
Min. Read/Write Cycle Time (tRC)
The IS41C16256 is packaged in a 40-pin 400mil SOJ and
400mil TSOP-2.
-25(5V)
-35
-50
-60 Unit
25 35 50 60 ns
10 10 14 15 ns
12 18 25 30 ns
10 12 20 25 ns
45 60 90 110 ns
PIN CONFIGURATIONS
40-Pin TSOP-2
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
1
2
3
4
5
6
7
8
9
10
40 GND
39 I/O15
38 I/O14
37 I/O13
36 I/O12
35 GND
34 I/O11
33 I/O10
32 I/O9
31 I/O8
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
11
12
13
14
15
16
17
18
19
20
30 NC
29 LCAS
28 UCAS
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21 GND
40-Pin SOJ
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 GND
39 I/O15
38 I/O14
37 I/O13
36 I/O12
35 GND
34 I/O11
33 I/O10
32 I/O9
31 I/O8
30 NC
29 LCAS
28 UCAS
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21 GND
PIN DESCRIPTIONS
A0-A8
I/O0-15
WE
OE
RAS
UCAS
LCAS
Vcc
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Power
Ground
No Connection
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
DR001-0E 01/25/2002
1




41C16256 pdf, 반도체, 판매, 대치품
wwIwS.D4a1taSChe1et64U2.c5om6
IS41LV16256
FunctionalDescription
The IS41C16256 and IS41LV16256 is a CMOS DRAM
optimized for high-speed bandwidth, low power applica-
tions. During READ or WRITE cycles, each bit is uniquely
addressed through the 18 address bits. These are en-
tered 9 bits (A0-A8) at a time. The row address is latched
by the Row Address Strobe (RAS). The column address
is latched by the Column Address Strobe (CAS). RAS is
used to latch the first nine bits and CAS is used the latter
nine bits.
The IS41C16256 and IS41LV16256 has two CAS controls,
LCAS and UCAS. The LCAS and UCAS inputs internally
generates a CAS signal functioning in an identical man-
ner to the single CAS input on the other 256K x 16
DRAMs. The key difference is that each CAS controls its
corresponding I/O tristate logic (in conjunction with OE
and WE and RAS). LCAS controls I/O0 through I/O7 and
UCAS controls I/O8 through I/O15.
The IS41C16256 and IS41LV16256 CAS function is
determined by the first CAS (LCAS or UCAS) transitioning
LOW and the last transitioning back HIGH. The two CAS
controls give the IS41C16256 both BYTE READ and
BYTE WRITE cycle capabilities.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time specified
by tAR. Data Out becomes valid only when tRAC, tAA, tCAC
and tOEA are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid
at or before the falling edge of CAS or WE, whichever
occurs first.
Refresh Cycle
To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memory.
1. By clocking each of the 512 row addresses (A0 through
A8) with RAS at least once every 8 ms. Any read, write,
read-modify-write or RAS-only cycle refreshes the
addressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Extended Data Out Page Mode
EDO page mode operation permits all 512 columns within
a selected row to be randomly accessed at a high data
rate.
In EDO page mode read cycle, the data-out is held to the
next CAS cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAS cycle time becomes shorter. Therefore,
in EDO page mode, the timing margin in read cycle is
larger than that of the fast page mode even if the CAS cycle
time becomes shorter.
In EDO page mode, due to the extended data function, the
CAS cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write opera-
tions during one RAS cycle, but the performance is
equivalent to that of the fast page mode in that case.
Power-On
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS signal).
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
4 Integrated Circuit Solution Inc.
DR001-0E 01/25/2002

4페이지










41C16256 전자부품, 판매, 대치품
w w w .IDSa4t a1SCh e1e6t 42U5.6c o m
IS41LV16256
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
tRC
tRAC
tCAC
tAA
tRAS
tRP
tCAS
tCP
tCSH
tRCD
tASR
tRAH
tASC
tCAH
tAR
tRAD
tRAL
tRPC
tRSH
tCLZ
tCRP
tOD
tOE
tOEHC
tOEP
tOES
tRCS
tRRH
tRCH
tWCH
tWCR
tWP
tWPZ
tRWL
tCWL
tWCS
tDHR
Parameter
-25 -35
Min. Max. Min. Max.
Random READ or WRITE Cycle Time
Access Time from RAS(6, 7)
Access Time from CAS(6, 8, 15)
45 —
— 25
— 10
Access Time from Column-Address(6)
RAS Pulse Width
RAS Precharge Time
CAS Pulse Width(26)
CAS Precharge Time(9, 25)
CAS Hold Time (21)
RAS to CAS Delay Time(10, 20)
— 12
25 10K
15 —
4 10K
4—
25 —
10 17
Row-Address Setup Time
0—
Row-Address Hold Time
6—
Column-Address Setup Time(20)
0—
Column-Address Hold Time(20)
5—
Column-Address Hold Time
(referenced to RAS)
19 —
RAS to Column-Address Delay Time(11) 8 20
Column-Address to RAS Lead Time
12 —
RAS to CAS Precharge Time
0—
RAS Hold Time(27)
7—
CAS to Output in Low-Z(15, 29)
3—
CAS to RAS Precharge Time(21)
5—
Output Disable Time(19, 28, 29)
2 12
Output Enable Time(15, 16)
OE HIGH Hold Time from CAS HIGH
OE HIGH Pulse Width
OE LOW to CAS HIGH Setup Time
08
10 —
10 —
5—
Read Command Setup Time(17, 20)
0—
Read Command Hold Time
(referenced to RAS)(12)
0—
Read Command Hold Time
(referenced to CAS)(12, 17, 21)
0—
Write Command Hold Time(17, 27)
5—
Write Command Hold Time
(referenced to RAS)(17)
19 —
Write Command Pulse Width(17)
WE Pulse Widths to Disable Outputs
Write Command to RAS Lead Time(17)
Write Command to CAS Lead Time(17, 21)
5
10
7
5
Write Command Setup Time(14, 17, 20)
0—
Data-in Hold Time (referenced to RAS) 19 —
60 —
— 35
— 10
— 18
35 10K
20 —
6 10K
5—
35 —
11 28
0—
6—
0—
6—
30 —
10 20
18 —
0—
8—
3—
5—
3 12
0 10
10 —
10 —
5—
0—
0—
0—
5—
30 —
5—
10 —
8—
8—
0—
30 —
-50 -60
Min. Max. Min. Max. Units
90 — 110 —
— 50 — 60
— 14 — 15
— 25 — 30
50 10K 60 10K
30 — 40 —
8 10K 10 10K
8 — 10 —
50 — 60 —
19 36 20 45
0— 0—
8 — 10 —
0— 0—
8 — 10 —
40 — 40 —
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
14 25
25 —
0—
14 —
3—
5—
3 12
0 15
10 —
10 —
5—
0—
0—
15 30
30 —
0—
15 —
3—
5—
3 12
— 15
10 —
10 —
5—
0—
0—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0 — 0 — ns
8—
40 —
10 —
50 —
ns
ns
8—
10 —
14 —
14 —
0—
40 —
10 —
10 —
15 —
15 —
0—
40 —
ns
ns
ns
ns
ns
ns
Integrated Circuit Solution Inc.
DR001-0E 01/25/2002
7

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관련 데이터시트

부품번호상세설명 및 기능제조사
41C16256

IS41C16256

Integrated Circuit Solution
Integrated Circuit Solution
41C16257

256K x 16 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE

Integrated Silicon Solution  Inc
Integrated Silicon Solution Inc

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