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AK2572 데이터시트 PDF




AKM에서 제조한 전자 부품 AK2572은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 AK2572 기능
기능 APC for Burst Mode Applicable Direct Modulation Laser Diode
제조업체 AKM
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AK2572 데이터시트, 핀배열, 회로
ASAHI KASEI
[AK2572]
AK2572
APC for Burst Mode Applicable Direct Modulation Laser Diode
FEATURES
Temperature compensation programming function
(APC_FF) of Bias current (0~85mA) and Modulation
current (0~10mA/0~2.2V) responding to the detected
temperature by the On-chip temperature sensor.
Stable feedback function in the digital scheme
(APC_FB).
SFP support TXFAULT function and 1k bit ID field
www.DataShe(EetE4UP.RcoOmM UserArea).
LD Power leveling function by either Hardware pin
control or Register setting.
Various alarm functions of Optical output decline
(OPTALM), Excessive LD current (CURRALM),
Exceptional temperature (TEMPALM) and Irregular
externalsignals (EXTALM1andEXTALM2).
Operation adjustment function via 2-wire Digital
interface after assembled into sub-system.
On-chipOscillatorallows a Self-runningoperation.
Single3.3V[Typ.]powersupply.
APPLICATIONS
ForLDmodulesappliedtoContinuous andBurstmode
OUTLINES
The AK2572 enables to keep the optical power of the direct
modulation LD (Laser Diode) constant by the APC
(Automatic Power Control) circuit. It consists of a current
programming function (APC_FF) responding to the
temperature characteristics of each LD, and a Digital
feedback function (APC_FB) to adjust the LD current
basedonthemonitoringPD (PhotoDiode)current.
The AK2572 is also applicable to the Burst mode
transmission. The device equips a Power leveling function
to switch a temperature compensation programming data
byeitherHardwarepin controlorRegistersetting.
The On-chip EEPROM (Non-volatile memory) allows to
adjust and to keep the individual setting data for each LD
characteristics via 2-wire Digital interface after being
assembled into sub-system. As 1k bits User Area is
allocated in the EEPROM, which supports the ID field of
the SFP specification, a proper operation required for the
SFPmoduleisrealizedbyusingtheTXFAULT function.
ORDERING GUIDE
Product Number
AK2572
Package Type
QFN28 5.2mm×5.2mm
BLOCK DIAGRAM
AVDD AVSS DVDD DVSS VDDMD VDDBI VSSBI
TEMPMON
PDMON
Monitor PD
Cpd Rpd
BIAS
RB (12k)
TEMP
-SENS
R_TEMP
ADC
PDGAIN
PDIN
BURST
EXTALM2/MOD_CTRL
EXTALM1
BIAS_GEN
OSC
EEPROM
I-DAC1
APC V-DAC3
IOUT1
VOUT3
I-DAC2
IOUT2
ALM Detection
TEMPALM
CURRALM
OPTALM
EXTALM2
EXTALM1
BIAS
MON
(x0.012)
2-wire Digital I/F
SHUTDOW N
CONTROL
Imod
LDD LD
Vmod
Ibias
BIASMON
TXFAULT*
TXDIS
*:Open Drain
**:Internally Pulled-up TEST1 TEST2 TEST3 TEST4 SCL SDA* W P**
<MS0290-E-01>
-1-
2004/8




AK2572 pdf, 반도체, 판매, 대치품
ASAHI KASEI
[AK2572]
I. PIN DESCRIPTION
Each symbol at I/ O column in the following table means,
PWR : PowerVDDor VSS, Ai : Analog input, Ao : Analog output,
Di : Digital input, Di_pu : Digital input with pulled-up resistor,
Do : Digital output, Do_od : Digital output (Open drain), Dio_od : Digital input/output (Open drain)
Pin# Pin Name
Function
I/O Note
1 TEST1 Input pin for AKM test. Connect it to DVSS for Normal operation.
2 TEST2 Input pin for AKM test. Connect it to DVSS for Normal operation.
3 TEST3 Input pin for AKM test. Connect it to DVSS for Normal operation.
Di
Di
Di
Connect it
to DVSS
4 DVDD Power supply for Digital circuit.
PWR
5 DVSS Ground for Digital circuit.
PWR
Alarms such as Optical output decline (OPTALM), Excessive LD
current (CURRALM), Exceptional temperature (TEMPALM) and
Irregular external signals (EXTALM1 and EXTALM2) can be
www.DataSheet4U.com
selected by EEPROM / Register setting as target alarms available on
TXFAULT-pin output.
When any of the selected alarms (ALM) is detected, TXFAULT-pin
Connect it
6 TXFAULT becomes ”High-Z“ output, and it becomes “H“ level with a pulled-up Do_od to Pulled-up
resistor connection. This pin is open-drain type and should be
resistor
connected to DVDD via a 4.7k ~ 10kΩ resistor.
With RE_SFP_SET“0“ (SFP support mode setting), TXFAULT-
pin output is held at “H“ level when any of the selected alarms is
detected till the shutdown request is released by “H“ to “L“ transition
on TXDIS-pin.
Serial data input / output pin for Digital interface.
Connect it
7 SDA This pin is open-drain type and should be connected to DVDD via a Dio_od to Pulled-up
4.7k ~ 10kΩ resistor.
resistor
8 SCL Serial clock input for Digital interface
Di
Should not
be left open
9
BURST
Burst signal input. It is active during “H“ input period (valid data
period). When this pin is not used, connect it to DVSS.
Di
Should not
be left open
When this pin is at “H“ input, Bias current DAC (I-DAC2) output
and Modulation current DAC (I-DAC1 or V-DAC3) output are
disabled. Refer to Table 7-1 and Table 7-2.
10
TXDIS
At RE_SFP_SET“0“ (SFP support mode setting), a logical sum of
TXFAULT output and TXDIS-pin input become a disable request.
Di
Should not
be left open
At RE_SFP_SET“1“, TXDIS-pin input becomes a disable request.
When this pin is externally pulled-up, use a higher than 4.7kΩ
resistor. When this pin is not used, connect it to DVSS.
11 AVDD Power supply for Analog circuit.
PWR
12 AVSS Ground for Analog circuit.
PWR
Monitoring PD (Photo Diode) voltage input.
The detected monitor PD current is I to V converted by external
13
PDIN
resistor and capacitor. Please adjust the cut-off frequency of an LPF
to be within 5k ~ 10kHz which is composed of external resistor (Rpd)
Ai
and capacitor (Cpd).
When this pin is not used, it is recommended to connect it to AVSS.
Bias current monitor. A current multiplied by 0.012 [Typ.] of the
14
BIASMON
I-DAC2 output current is sourced from this pin. When to convert the
current to a voltage by an external resistor, select the resistor value
Ao
such that BIASMON-pin voltage1.3 V.
15 VSSBI Ground for I-DAC2.
PWR
<MS0290-E-01>
-4-
2004/8

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AK2572 전자부품, 판매, 대치품
ASAHI KASEI
[AK2572]
(4) Digital Input / Output Pin AC Characteristics (Serial Interface)
tF
tR
SCL
SDA (IN)
tSU.STA
tHD.STA
tAA
tHD.DAT
tSU.STO
tSU.DAT
tDH tBUF
www.DataSheSetD4UA.co(mOUT)
Symbol
Parameter
Min.
SCL
Clock Frequency, SCL
LOW
Clock Pulse Width Low
4.7
HIGH
Clock Pulse Width High
4.0
I Noise Suppression Time
AA Clock Low to Data Out Valid 0.1
BUF
Time before a New Transmission
4.7
HD.STA
Start Hold Time
4.0
SU.STA
Start Setup Time
4.7
HD.DAT
Data Hold Time
0
SU.DAT
Data Setup Time
200
R Input Rise Time
F Input Fall Time
SU.STO
Stop Setup Time
4.0
DH
Data Out Hold Time
100
WR Write Cycle Time
[*] This parameter is characterized and is not 100% tested.
Max.
100
100
4.5
1.0
0.3
10
Unit
kHz
μs
μs
ns
μs
μs
μs
μs
μs
ns
μs
μs
μs
ns
ms
Note
[*]
[*]
<MS0290-E-01>
-7-
2004/8

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