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PDF KM4132G512A Data sheet ( Hoja de datos )
| Número de pieza | KM4132G512A | |
| Descripción | 256K X 32Bit X 2 Banks Synchronous Graphic RAM | |
| Fabricantes | Samsung semiconductor | |
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KM4132G512A
CMOS SGRAM
www.DataSheet4U.com
16Mbit SGRAM
256K x 32bit x 2 Banks
Synchronous Graphic RAM
LVTTL
Revision 1.2
July 1999
Samsung Electronics reserves the right to change products or specification without notice.
- 1 - Rev. 1.2 (Jul. 1999)
1 page  
KM4132G512A
CMOS SGRAM
ABSOLUTE MAXIMUM RATINGS(Voltage referenced to VSS)
Parameter
Symbol
Value
Voltage on any pin relative to Vss
VIN, VOUT
-1.0 ~ 4.6
Voltage on VDD supply relative to Vss
VDD, VDDQ
-1.0 ~ 4.6
Storage temperature
TSTG
-55 ~ +150
Power dissipation
PD 1
Short circuit current
IOS 50
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V)
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Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VDD, VDDQ
3.0
3.3
3.6
V
Input high voltage
VIH
2.0
3.0 VDDQ+0.3
V
Input low voltage
VIL -0.3
0
0.8
V
Output high voltage
VOH
2.4
-
-
V
Output low voltage
VOL
-
- 0.4 V
Input leakage current
ILI -10
-
10 uA
Output leakage current
ILO -10
-
10 uA
Output Loading Condition
see figure 1
Note : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V ≤ VOUT ≤ VDD.
5. The VDD condition of KM4132G512A-5/C/6 is 3.135V~3.6V.
Unit
V
V
°C
W
mA
Note
5
1
2
IOH = -2mA
IOL = 2mA
3
4
CAPACITANCE (VDD/VDDQ = 3.3V, TA = 23°C, f = 1MHz)
Pin Symbol
Clock
CCLK
RAS, CAS, WE, CS, CKE, DQMi,DSF
CIN
Address
CADD
DQi COUT
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Min
-
-
-
-
Parameter
Symbol
Decoupling Capacitance between VDD and VSS
CDC1
Decoupling Capacitance between VDDQ and VSSQ
CDC2
Note : 1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
Max
4.0
4.0
4.0
5.0
Value
0.1 + 0.01
0.1 + 0.01
Unit
pF
pF
pF
pF
Unit
uF
uF
- 5 - Rev. 1.2 (Jul. 1999)
5 Page 
KM4132G512A
CMOS SGRAM
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Function
RFU W.B.L
(Note 1) (Note 2)
TM
CAS Latency BT Burst Length
Test Mode
CAS Latency
A8 A7
Type
A6 A5 A4 Latency
0 0 Mode Register Set 0 0 0 Reserved
01
Vendor
10
Use
Only
11
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Write Burst Length
001
010
011
100
-
2
3
Reserved
A9 Length
1 0 1 Reserved
0 Burst 1 1 0 Reserved
1 Single Bit 1 1 1 Reserved
Burst Type
A3 Type
0 Sequential
1 Interleave
Burst Length
A2 A1 A0
BT=0
000
1
001
2
010
4
011
8
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 256(Full)
BT=1
Reserved
Reserved
4
8
Reserved
Reserved
Reserved
Reserved
(Note 3)
Special Mode Register Programmed with SMRS
Address
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Function
X
LC LM
X
Load Color
A6 Function
0 Disable
1 Enable
Load Mask
A5 Function
0 Disable
1 Enable
POWER UP SEQUENCE
SGRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 may be changed.
The device is now ready for normal operation.
Note : 1. RFU(Reserved for Future Use) should stay "0" during MRS cycle.
2. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
3. The full column burst(256bit) is available only at Sequential mode of burst type.
4. If LC and LM both high(1), data of mask and color register will be unknown.
- 11 Rev. 1.2 (Jul. 1999)
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