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PDF M30620MCN Data sheet ( Hoja de datos )
| Número de pieza | M30620MCN | |
| Descripción | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER | |
| Fabricantes | Mitsubishi Electric | |
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Rev.1.0
Description
Mitsubishi microcomputers
M16C / 62N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
The M16C/62N group of single-chip microcomputers are built using the high-performance silicon gate
CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP.
These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruc-
tion efficiency. With 1M bytes of address space, low voltage (2.4V(mask ROM version is 2.2V) to 3.6V),
they are capable of executing instructions at high speed. They also feature a built-in multiplier and DMAC,
making them ideal for controlling office, communications, industrial equipment, and other high-speed pro-
cessing applications.
The M16C/62N group includes a wide range of products with different internal memory types and sizes and
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various package types.
Features
• Memory capacity .................................. ROM (See Figure 1.1.4. ROM Expansion)
RAM 10K to 20K bytes
• Shortest instruction execution time ...... 62.5ns (f(XIN)=16MHZ, VCC=3.0V to 3.6V)
142.9ns (f(XIN)=7MHZ, VCC=2.4V to 3.6V without software wait)
• Supply voltage ..................................... 3.0V to 3.6V (f(XIN)=16MHZ, without software wait)
2.4V to 3.0V (f(XIN)=7MHZ, without software wait)
2.2V to 3.0V (f(XIN)=7MHZ, with software one-wait) :mask ROM version
• Low power consumption ...................... 34.0mW (VCC = 3V, f(XIN)=10MHZ, without software wait)
66.0mW (VCC = 3.3V, f(XIN)=16MHZ, without software wait)
• Interrupts .............................................. 25 internal and 8 external interrupt sources, 4 software
interrupt sources; 7 levels (including key input interrupt)
• Multifunction 16-bit timer ...................... 5 output timers + 6 input timers
• Serial I/O .............................................. 5 channels (3 for UART or clock synchronous, 2 for clock synchro-
nous)
• DMAC .................................................. 2 channels (trigger: 24 sources)
• A-D converter ....................................... 10 bits X 8 channels (Expandable up to 18 channels)
• D-A converter ....................................... 8 bits X 2 channels
• CRC calculation circuit ......................... 1 circuit
• Watchdog timer .................................... 1 line
• Programmable I/O ............................... 87 lines
_______
• Input port .............................................. 1 line (P85 shared with NMI pin)
• Memory expansion .............................. Available (to 4M bytes)
• Chip select output ................................ 4 lines
• Clock generating circuit ....................... 2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
Applications
Audio, cameras, office equipment, communications equipment, portable equipment
------Table of Contents------
Central Processing Unit (CPU) ..................... 11
Timer ............................................................. 81
Reset ............................................................. 14
Serial I/O ..................................................... 111
Processor Mode ............................................ 25
A-D Converter ............................................. 152
Clock Generating Circuit ............................... 39
D-A Converter ............................................. 162
Protection ...................................................... 48
CRC Calculation Circuit .............................. 164
Interrupts ....................................................... 49
Programmable I/O Ports ............................. 166
Watchdog Timer ............................................ 69
Electrical characteristics ............................. 176
DMAC ........................................................... 71
Flash memory version ................................. 191
1
1 page  
Description
Mitsubishi microcomputers
M16C / 62N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Performance Outline
Table 1.1.1 is a performance outline of M16C/62N group.
Table 1.1.1. Performance outline of M16C/62N group
Item
Number of basic instructions
Shortest instruction execution time
Memory
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capacity
ROM
RAM
I/O port
P0 to P10 (except P85)
Input port P85
Multifunction TA0, TA1, TA2, TA3, TA4
timer
TB0, TB1, TB2, TB3, TB4, TB5
Serial I/O UART0, UART1, UART2
SI/O3, SI/O4
A-D converter
D-A converter
DMAC
CRC calculation circuit
Watchdog timer
Interrupt
Clock generating circuit
Supply voltage
Power consumption
I/O I/O withstand voltage
characteristics Output current
Memory expansion
Device configuration
Package
Performance
91 instructions
62.5ns(f(XIN)=16MHZ, VCC=3.0V to 3.6V)
142.9ns(f(XIN)=7MHZ, VCC=2.4V to 3.6V, without software wait)
(See the figure 1.1.4. ROM Expansion)
10K to 20K bytes
8 bits x 10, 7 bits x 1
1 bit x 1
16 bits x 5
16 bits x 6
(UART or clock synchronous) x 3
(Clock synchronous) x 2
10 bits x (8 x 2 + 2) channels
8 bits x 2
2 channels (trigger: 24 sources)
CRC-CCITT
15 bits x 1 (with prescaler)
25 internal and 8 external sources, 4 software sources, 7 levels
2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
3.0V to 3.6V (f(XIN)=16MHZ, without software wait)
2.4V to 3.0V (f(XIN)=7MHZ, without software wait)
2.2V to 3.0V (f(XIN)=7MHZ, with software one-wait):mask ROM version
34.0mW (VCC=3V, f(XIN)=10MHZ, without software wait)
66.0mW (VCC=3.3V, f(XIN)=16MHZ, without software wait)
3.3V
1mA
Available (to 4M bytes)
CMOS high performance silicon gate
100-pin plastic molded QFP
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5 Page 
CPU
Mitsubishi microcomputers
M16C / 62N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 1.4.1. Seven of these registers (R0, R1, R2, R3, A0,
A1, and FB) come in two sets; therefore, these have two register banks.
b15 b8 b7
b0
R0(Note)
H
L
b15 b8 b7
b0
www.DataSheet4U.coRm1(Note)
H
L
b15
R2(Note)
b0
Data
registers
b19
PC
b19
INTB H
b15
R3(Note)
b0
b15
USP
b15
A0(Note)
b15
A1(Note)
b0
Address
b0 registers
b15
ISP
b15
SB
b15
FB(Note)
b0
Frame base
registers
b15
FLG
L
b0
Program counter
b0
Interrupt table
register
b0
User stack pointer
b0
Interrupt stack
pointer
b0
Static base
register
b0
Flag register
IPL U I O B S Z D C
Note: These registers consist of two register banks.
Figure 1.4.1. Central processing unit register
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H),
and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can
use as 32-bit data registers (R2R0/R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address register
relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
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