|
|
PDF PL611-30 Data sheet ( Hoja de datos )
| Número de pieza | PL611-30 | |
| Descripción | Programmable Quick Turn Clock | |
| Fabricantes | PhaseLink Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de PL611-30 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
|
No Preview Available !
PPreliminary L611-30
Programmable Quick Turn ClockTM
FEATURES
• Advanced programmable PLL design
• Very low Jitter and Phase Noise (< 40ps Pk-Pk typical)
• Output frequency up to 375MHz CMOS.
• Supports differential CMOS output to produce PECL,
LVDS inputs.
• Crystal inputs:
o Fundamental crystal: 10MHz-30MHz
www.DataSheet4Uoo.comR3ReDfeorveenrctoenienpcurty:sUtapl:
Up to
to 200
75MHz
MHz
• Accepts <1.0V reference signal input voltage
• One programmable I/O pin can be configured as
Output Enable (OE), or Frequency Selection input
(FSEL), or Reference clock.
• Single 3.3V ± 10% power supply
• Operating temperature range from -40°C to 85°C
• Available in 8-pin MSOP/SOIC, 6-pin SOT Green/
RoHS compliant packages.
PIN CONFIGURATION
XIN/FIN
GND
CLK0
CLK1
18
27
36
45
SOP-8
MSOP-8
XOUT
CLK2, OE, FSEL
DNC
VDD
DESCRIPTION
The PL611-30 is a low-cost general purpose frequency synthesizer and a member of PhaseLink’s Factory
Programmable ‘Quick Turn Clock (QTC)’ family. PhaseLink’s PL611-30 product family can generate any output
frequency up to 375 MHz from fundamental crystal input between 10 MHz - 30 MHz, or a 3rd overtone crystal of
up to 75Mhz. The PL611-30 produces differential CMOS outputs to support PECL, LVDS, and CMOS inputs.
BLOCK DIAGRAM
XIN/FIN
XOUT
Xtal
OSC
FRef
.
R- counter
M-counter
( 6 -bit)
Phase
Detector
Charge
Pump
FSEL
OE
CLoad
FVCO = F Ref. * (2 * M /R)
P-counter
(5-bit)
VCO
FOut = FVCO / (2 * P)
Loop
Filter
Programmable Function
/1, /2
CLK[0:1]
CLK2
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 1
1 page  
PPreliminary L611-30
Programmable Quick Turn ClockTM
Figure 1 below describes how to terminate the differential CMOS outputs of PhaseLink’s PL611-30 Programmable QTC clock
for use with PECL or LVDS inputs.
The unique feature of differential CMOS outputs allows great flexibility for board designers. By standardizing on one termination
scheme you can use the PL611-30 for all your LVDS and PECL clock requirements up to 375MHz.
www.DataSheet4U.com
CMOS Output
R1
50Ω line
+3.3V
R2
Input
R3
Complementary
CMOS Output
R1
50Ω line
3.3V
R3
R2
Complementary
Input
PECL LVDS
2.35V 1.40V
0V +3.3V
1.59V 1.10V
Component selection
For PECL input For LVDS input
R1 = 130Ω
R2 = 82Ω
R3 = 130Ω
R1 = 360Ω
R2 = 82Ω
R3 = 130Ω
Notes:
Place R1 as close to the CMOS outputs as
possible.
Place R2 and R3 as close to the PECL/LVDS
inputs as possible.
Figure 1
The above layout allows the PL611-30 to drive either a PECL or LVDS input by simply changing the value of R1.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet PL611-30.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| PL611-30 | Programmable Quick Turn Clock | PhaseLink Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |