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PDF PL611S-17 Data sheet ( Hoja de datos )
| Número de pieza | PL611S-17 | |
| Descripción | PicoPLLTM KHz to MHz Programmable Clock | |
| Fabricantes | PhaseLink Corporation | |
| Logotipo |  |
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P(Preliminary) L611s-17
1.8V-3.3V PicoPLLTM KHz to MHz Programmable Clock
FEATURES
• Advanced Programmable PLL design for low-
frequency (kHz) input applications.
• Input Frequency: 10kHz to 200MHz
• OTP selectable AC/DC Input Coupling.
• Accepts >0.1V reference signal input voltage
• Very low Jitter and Phase Noise
• Output Frequency:
www.DataSheet4U.coom <65MHz @ 1.8V operation
o <90MHz @ 2.5V operation
o <125MHz @ 3.3V operation
• Disabled outputs programmable as HiZ or Active Low.
• Offered in Tiny GREEN/RoHS compliant packages
o 6-pin DFN (2.0mmx1.3mmx0.6mm)
o 6-pin SC70 (2.3mmx2.25mmx1.0mm)
o 6-pin SOT23 (3.0mmx3.0mmx1.35mm)
• Single 1.8V, 2.5V, or 3.3V ± 10% power supply
• Operating temperature range from -40°C to 85°C
DESCRIPTION
The PL611s-17 is a low-cost general purpose
frequency synthesizer and a member of PhaseLink’s
PicoPLLTM Factory Programmable ‘Quick Turn Clock
(QTC)’ family. Designed to fit in a small SOT23,
SC70, or DFN package for high performance, low
power applications, the PL611s-17 accepts a low
frequency (>10KHz) Reference input and generates
up to 125MHz outputs with the best phase noise,
jitter performance, and power consumption for
handheld devices and notebook applications. In
addition, one programmable I/O pin can be
configured as Output Enable (OE), Frequency
switching (FSEL), Power Down (PDB) input, or CLK1
(FOUT, FREF, FREF/2) output. Cascading the PL611s-
17 with other PicoPLL ICs can result in producing all
required system clocks with specific savings in board
space, power consumption, and cost.
PACKAGE PIN CONFIGURATION
FIN
OE, PDB, FSEL, CLK1
VDD
1
2
3
6 LF
5 GND
4 CLK0
DFN-6L
(2.0mmx1.3mmx0.6mm)
OE, PDB,
FSEL, CLK1
1
6
CLK0
VDD 2 5 GND
FIN 3 4 LF
SC70-6L
(2.3mmx2.25mmx1.0mm)
LF
GND
CLK0
1
2
3
6 FIN
5
OE, PDB,
FSEL, CLK1
4 VDD
SOT23-6L
(3.0mmx3.0mmx1.35mm)
BLOCK DIAGRAM
FIN
Ref. R-Counter
(7-bit)
Phase
M-Counter
Detector
(16-bit)
FVCO = FRef * (M/R)
Charge
Pump
VCO
Programmable
Function
P-Counter
FOut = FVCO /2*P (4-bit)
Programming
Logic
CLK0
OE, PDB,
FSEL, CLK1
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/04/07 Page 1
1 page  
P(Preliminary) L611s-17
1.8V-3.3V PicoPLLTM KHz to MHz Programmable Clock
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage Range
VDD -0.5
7
V
Input Voltage Range
VI
-0.5 VDD+0.5
V
Output Voltage Range
VO
-0.5 VDD+0.5
V
Soldering Temperature (Green package)
www.DataSheet4U.com
Data Retention @ 85°C
260 °C
10 Year
Storage Temperature
TS -65 150 °C
Ambient Operating Temperature*
-40 85 °C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
Input (FIN) Frequency
Input (FIN) Signal Amplitude
Input (FIN) Signal Amplitude
Output Frequency
Settling Time
Output Enable Time
CONDITIONS
@ VDD =3.3V
@ VDD =2.5V
@ VDD =1.8V
Internally AC/DC coupled (High Frequency)
Internally AC/DC coupled (Low Frequency)
3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz
@ VDD =3.3V
@ VDD =2.5V
@ VDD =1.8V
At power-up (after VDD increases over 1.62V)
OE Function; Ta=25º C, 15pF Load
PDB Function; Ta=25º C, 15pF Load
Output Rise Time
Output Fall Time
15pF Load, 10/90% VDD, High Drive, 3.3V
15pF Load, 90/10% VDD, High Drive, 3.3V
Duty Cycle
VDD /2
Period Jitter, Pk-to-Pk*
With capacitive decoupling between VDD and
(measured from 10,000 samples) GND.
* Note: Jitter performance depends on the programming parameters.
MIN. TYP. MAX. UNITS
200
10KHz
166 MHz
133
0.9 VDD Vpp
0.1 VDD Vpp
125
90 MHz
65
2 ms
10 ns
2 ms
1.2 1.7 ns
1.2 1.7 ns
45 50 55 %
70 ps
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/04/07 Page 5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet PL611S-17.PDF ] | |
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