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PDF PL611S-26 Data sheet ( Hoja de datos )

Número de pieza PL611S-26
Descripción PicoPLLTM Programmable Clock
Fabricantes PhaseLink Corporation 
Logotipo PhaseLink Corporation Logotipo



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No Preview Available ! PL611S-26 Hoja de datos, Descripción, Manual

P(Preliminary) L611s-26
1.8V-3.3V PicoPLLTM Programmable Clock
FEATURES
Advanced One Time Programmable (OTP) PLL design
Programmable PLL or direct oscillation operation
Very low Jitter and Phase Noise (30-70ps Pk-Pk
typical)
Output Frequency up to
o 133MHz @ 1.8V operation
o 166MHz @ 2.5V operation
www.DataSheet4U.coom200MHz @ 3.3V operation
Reference Input Frequency: 1MHz to 200MHz
Accepts >0.1V reference signal input voltage
Low current consumption, <10µA when PDB is
activated
One programmable I/O pin can be configured as
Output Enable (OE),Power Down (PDB) input or an
additional clock output (CLK1).
Frequency Switching (FSEL) capability
Single 1.8V, 2.5V, or 3.3V ± 10% power supply
Operating temperature range from -40°C to 85°C
Available in 6-pin SOT23 and DFN GREEN/RoHS
compliant packaging
DESCRIPTION
The PL611s-26 is a general purpose frequency
synthesizer and a member of PhaseLink’s PicoPLLTM
product family. Designed to fit in a small 6-pin DFN
or 6-pin SOT package for high performance
applications, the PL611s-26 offers very low phase
noise, jitter, and power consumption, while offering
up to 2 clock outputs.. The Frequency Switching
(FSEL) capability of PL611s-26 allows for
programming two sets of frequencies, while the
power down feature of PL611s-26, when activated,
allows the IC to consume less than 10µA of power.
PL611s-26’s programming flexibility allows
generating any output using Reference input signal.
BLOCK DIAGRAM
FIN
FREF R-Counter
(8-bit)
Phase
M-Counter
Detector
(11-bit)
Charge
Pump
FVCO = FREF * (2 * M/R)
Programmable Function
P-Counter
FOUT = FVCO / (2 * P) (5-bit)
Programming
Logic
Loop
Filter
VCO
CLK0
FSEL
OE, PDB,
CLK1
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 1

1 page




PL611S-26 pdf
P(Preliminary) L611s-26
1.8V-3.3V PicoPLLTM Programmable Clock
DC SPECIFICATIONS
PARAMETERS
SYMBOL
CONDITIONS
Supply Current, Dynamic, with
Loaded CMOS Outputs
Supply Current, Dynamic, with
Loaded CMOS Outputs
Supply Current, Dynamic with
www.DataSheeLt4oUa.dcoemd CMOS Outputs
Stand By Current, with Loaded
Outputs
Operating Voltage
Output Low Voltage
Output High Voltage
Output Current, Low Drive
Output Current, Standard Drive
Output Current, High Drive
IDD
@ VDD =3.3V, 27MHz,
load=15pF
IDD
@ VDD =2.5V, 27MHz,
load=15pF
IDD
@ VDD =1.8V, 27MHz,
load=15pF
IDD When PDB=0
VDD
VOL IOL = +4mA Standard Drive
VOH IOH = -4mA Standard Drive
IOSD VOL = 0.4V, VOH = 2.4V
IOSD VOL = 0.4V, VOH = 2.4V
IOHD VOL = 0.4V, VOH = 2.4V
* Note: Please contact PhaseLink, if super low-power is required.
MIN.
1.62
VDD – 0.4
4
8
16
TYP.
5.5
3.8
1.8*
MAX.
<10
3.63
0.4
UNITS
mA
mA
mA
µA
V
V
V
mA
mA
mA
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 5

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