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PL611S-27 데이터시트 PDF




PhaseLink Corporation에서 제조한 전자 부품 PL611S-27은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 PL611S-27 기능
기능 PicoPLLTM Programmable Clock
제조업체 PhaseLink Corporation
로고 PhaseLink Corporation 로고


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PL611S-27 데이터시트, 핀배열, 회로
P(Preliminary) L611s-27
1.8V to 3.3V PicoPLLTM Programmable Clock
FEATURES
Advanced One Time Programmable (OTP) PLL design
Programmable PLL or direct oscillation operation
Very low Jitter and Phase Noise (30-70ps Pk-Pk typical)
Output Frequency up to
o 65MHz @ 1.8V operation
o 9/MHz @ 2.5V operation
o 125MHz @ 3.3V operation
Reference Input Frequency: 1MHz to 200MHz
www.DataSheet4UA.ccocmepts >0.1V reference signal input voltage
Low current consumption, <10µA when PDB is
activated
One programmable I/O pin can be configured as
Output Enable (OE), Frequency Switching
(FSEL), or Power Down (PDB) input.
Disabled outputs programmable as HiZ or Active Low.
Single 1.8V, 2.5V, or 3.3V ± 10% power supply
Operating temperature range from 0°C to 70°C
Available in 6-pin SOT23 & DFN GREEN/RoHS
Compliant packages
DESCRIPTION
The PL611s-27 is a general purpose frequency
synthesizer and a member of PhaseLink’s PicoPLL
product family. Designed to fit in a small 6-pin DFN,
or 6-pin SOT package for high performance
applications, the PL611s-27 offers very low phase
noise, jitter, and power consumption, while offering 2
clock outputs. The Frequency Switching (FSEL)
capability of PL611s-27 allows for programming two
sets of frequencies, while the power down feature of
PL611s-27, when activated, allows the IC to
consume less than 10µA of power. PL611s-27’s
programming flexibility allows generating any output
using a Reference input signal.
PACKAGE PIN CONFIGURATION
FIN 1
CLK1 2
GND 3
6 OE, PDB, FSEL
5 VDD
4 CLK0
CLK1
GND
FIN
1
2
3
6 CLK0
5 VDD
4 OE, PDB, FSEL
DFN-6L
(2.0mmx1.3mmx0.6mm)
SOT23-6L
(3.0mmx3.0mmx1.35mm)
BLOCK DIAGRAM
FIN
Fref R-counter
(8-Bit)
M-counter
(11-Bit)
Phase
Detector
Fvco=Fref* (2 * M /R)
Charge
Pump
Loop
Filter
VCO
P-counter
(5-Bit) Fout=FVCO/(2*P)
CLK1
CLK0
Programmable Function
Programming
Logic
OE, PDB,
FSEL
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/25/07 Page 1




PL611S-27 pdf, 반도체, 판매, 대치품
P(Preliminary) L611s-27
1.8V to 3.3V PicoPLLTM Programmable Clock
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage Range
Input Voltage Range
Output Voltage Range
www.DataSheetS4oUl.dceorming Temperature (Green package)
VDD -0.5
7
V
VI
-0.5 VDD+0.5
V
VO
-0.5 VDD+0.5
V
260 °C
Data Retention @ 85°C
10 Year
Storage Temperature
TS -65 150 °C
Ambient Operating Temperature*
-40 85 °C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
CONDITIONS
@ VDD =3.3V
Input (FIN) Frequency
@ VDD =2.5V
@ VDD =1.8V
Input (FIN) Signal Amplitude
Input (FIN) Signal Amplitude
Internally AC coupled (High Frequency)
Internally AC coupled (Low Frequency)
3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz
@ VDD =3.3V
Output Frequency
@ VDD =2.5V
@ VDD =1.8V
Settling Time
At power-up (after VDD increases over 1.62V)
Output Enable Time
OE Function; Ta=25º C, 15pF Load
PDB Function; Ta=25º C, 15pF Load
Output Rise Time
15pF Load, 10/90% VDD, High Drive, 3.3V
Output Fall Time
15pF Load, 90/10% VDD, High Drive, 3.3V
Duty Cycle
VDD /2
Period Jitter,Pk-to-Pk*
With capacitive decoupling between VDD and
(measured from 10,000 samples) GND.
* Note: Jitter performance depends on the programming parameters.
MIN. TYP. MAX. UNITS
200
1 166 MHz
133
0.9 VDD Vpp
0.1 VDD Vpp
125 MHz
90 MHz
65 MHz
2 ms
10 ns
2 ms
1.2 1.7 ns
1.2 1.7 ns
45 50 55 %
70 ps
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/25/07 Page 4

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PL611S-27 전자부품, 판매, 대치품
P(Preliminary) L611s-27
1.8V to 3.3V PicoPLLTM Programmable Clock
Crystal Tuning Circuit
Series and parallel capacitors used to fine tune the crystal load to the circuit load .
Crystal
Cst
www.DataSheet4U.com
XIN
1
Cpt
XOUT
8
Cpt
CST – Series Capacitor, used to lower circuit load to match crystal load . Raises frequency
offset. This can be eliminated by using a crystal with a Cload of equal or greater value than the
oscillator.
CPT – Parallel Capacitors , Used to raise the circuit load to match the crystal load. Lowers
frequency offset .
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/25/07 Page 7

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