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PL611S-15 데이터시트 PDF




PhaseLink Corporation에서 제조한 전자 부품 PL611S-15은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 PL611S-15 자료 제공

부품번호 PL611S-15 기능
기능 PicoPLLTM 32K Programmable Clock
제조업체 PhaseLink Corporation
로고 PhaseLink Corporation 로고


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PL611S-15 데이터시트, 핀배열, 회로
P(Preliminary) L611s-15
1.8V-3.3V PicoPLLTM 32K Programmable Clock
FEATURES
Advanced Programmable PLL design for low-
frequency (KHz) input applications.
OTP selectable AC/DC Ref. Coupling.
Accepts <1.0V reference signal input voltage
Very low Jitter and Phase Noise (30-70ps Pk-Pk typical)
Output frequency up to
o 133MHz @ 1.8V operation
o 166MHz @ 2.5V operation
o 200MHz @ 3.3V operation
www.DataSheet4UO.cffoemred in Tiny GREEN/RoHS compliant packages
o 6-pin DFN (2.0mmx1.3mmx0.6mm)
o 6-pin SC70 (2.3mmx2.25mmx1.0mm)
o 6-pin SOT23 (3.0mmx3.0mmx1.35mm)
Input Frequency: 10KHz – 200MHz
Single 1.8V, 2.5V, or 3.3V ± 10% power supply
Operating temperature range from 0°C to 70°C
DESCRIPTION
The PL611s-15 is a low-cost general purpose
frequency synthesizer and a member of PhaseLink’s
PicoPLLTM Factory Programmable ‘Quick Turn Clock
(QTC)’ family. Designed to fit in a small SOT23,
SC70, or DFN package for high performance
applications, the PL611s-15 accepts low frequency
(>10KHz) Reference input and generates up to
200MHz output with the best phase noise, jitter
performance, and power consumption for handheld
devices and notebook applications. Cascading
PL611s-15 with other PicoPLL ICs could result in
producing all required system clocks with specific
savings in board space, power consumption, and
cost.
PACKAGE PIN ASSIGNMENT
FIN 1
GNDA 2
VDD 3
6 LF
5 GND
4 CLK0
DFN-6L
(2.0mmx1.3mmx0.6mm)
FIN 1 6 LF
GNDA 2 5 GND
VDD 3 4 CLK0
SC70-6L
(2.3mmx2.25mmx1.0mm)
VDD
GNDA
FIN
1
2
3
6 CLK0
5 GND
4 LF
SOT23-6L
(3.0mmx3.0mmx1.35mm)
BLOCK DIAGRAM
FIN
R-Counter
(7-bit)
Phase
Charge
M-Counter
Detector
Pump
(16-bit)
FVCO = FRef * (2* M/R)
VCO
Programmable Function
P-Counter
FOut = FVCO /2*P (4-bit)
CLK0
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 07/18/06 Page 1




PL611S-15 pdf, 반도체, 판매, 대치품
DC SPECIFICATIONS
P(Preliminary) L611s-15
1.8V-3.3V PicoPLLTM 32K Programmable Clock
PARAMETERS
SYMBOL
CONDITIONS
Supply Current, Dynamic, with
Loaded CMOS Outputs
Supply Current, Dynamic, with
Loaded CMOS Outputs
IDD
@Vdd=3.3V,30MHz,
load=15pF
IDD
@Vdd=2.5V,30MHz,
load=15pF
Supply Current, Dynamic with
Loaded CMOS Outputs
www.DataSheet4U.com
Operating Voltage
IDD
@Vdd=1.8V,30MHz,
load=5pF
VDD
Output Low Voltage
VOL IOL = +4mA Standard Drive
Output High Voltage
VOH IOH = -4mA Standard Drive
Output Current, Low drive
IOSD VOL = 0.4V, VOH = 2.4V
Output Current, Standard drive
IOSD VOL = 0.4V, VOH = 2.4V
Output Current, High drive
IOHD VOL = 0.4V, VOH = 2.4V
Short-circuit Current
IS
* Note: Please see PL611s-16 datasheet if lower power is required.
MIN.
1.62
VDD – 0.4
TYP.
6.0
3.9
2.1*
3.3
±50
MAX.
UNITS
mA
mA
mA
3.63 V
0.4 V
V
4 mA
8 mA
16 mA
mA
PCB LAYOUT CONSIDERATIONS FOR PERFORMANCE OPTIMIZATION
The following guidelines are to assist you with a performance optimized PCB design:
- Keep all the PCB traces to PL611s-15 as short
as possible, as well as keeping all other traces
as far away from it as possible.
- When a reference input clock is generated from
a crystal (see diagram above), place the
PL611s-15 ‘FIN’ as close as possible to the
‘Xout’ crystal pin. This will reduce the cross-
talk between the reference input and the other
signals.
- Place the Loop Filter (LF) components as close
to the package pin of PL611s-15 as possible.
- Place a 0.01µF~0.1µF decoupling capacitor
between VDD and GND, on the component
side of the PCB, close to the VDD pin. It is not
recommended to place this component on the
backside of the PCB. Going through vias will
reduce the signal integrity, causing additional
jitter and phase noise.
- It is highly recommended to keep the VDD and
GND traces as short as possible.
- When connecting long traces (> 1 inch) to a
CMOS output, it is important to design the
traces as a transmission line or ‘stripline’, to
avoid reflections or ringing. In this case, the
CMOS output needs to be matched to the trace
impedance. Usually ‘striplines’ are designed
for 50impedance and CMOS outputs usually
have lower than 50impedance so matching
can be achieved by adding a resistor in series
with the CMOS output pin to the ‘stripline’
trace.
- Please contact PhaseLink for the application
note on how to design outputs driving long
traces or the Gerber files for the PL611s-15
layout.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 07/18/06 Page 4

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관련 데이터시트

부품번호상세설명 및 기능제조사
PL611S-15

PicoPLLTM 32K Programmable Clock

PhaseLink Corporation
PhaseLink Corporation
PL611S-15

PicoPLLTM 32K Programmable Clock

PhaseLink Corporation
PhaseLink Corporation

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