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54LS374 데이터시트 PDF




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54LS374 데이터시트, 핀배열, 회로
May 1992
DM54LS373 DM74LS373
DM54LS374 DM74LS374
TRI-STATE Octal D-Type Transparent
Latches and Edge-Triggered Flip-Flops
General Description
www.DataSheet4U.com
These 8-bit registers feature totem-pole TRI-STATE outputs
designed specifically for driving highly-capacitive or relative-
ly low-impedance loads The high-impedance state and in-
creased high-logic level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for inter-
face or pull-up components They are particularly attractive
for implementing buffer registers I O ports bidirectional
bus drivers and working registers
(Continued)
Features
Y Choice of 8 latches or 8 D-type flip-flops in a single
package
Y TRI-STATE bus-driving outputs
Y Full parallel-access for loading
Y Buffered control inputs
Y P-N-P inputs reduce D-C loading on data lines
Connection Diagrams
Dual-In-Line Packages
’LS373
Order Number
DM54LS373J
DM54LS373W
DM74LS373N or
DM74LS373WM
See NS Package Number
J20A M20B N20A or
W20A
’LS374
TL F 6431 – 1
Order Number
DM54LS374J
DM54LS374W
DM74LS374WM or
DM74LS374N
See NS Package Number
J20A M20B N20A or
W20A
TRI-STATE is a registered trademark of National Semiconductor Corp
C1995 National Semiconductor Corporation TL F 6431
TL F 6431 – 2
RRD-B30M105 Printed in U S A




54LS374 pdf, 반도체, 판매, 대치품
‘LS373 Switching Characteristics at VCC e 5V and TA e 25 C
(See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From
(Input)
To
(Output)
RL e 667X
CL e 45 pF
CL e 150 pF
Min Max Min Max
tPLH
Propagation Delay
Time Low to High
Level Output
Data
to
Q
18 26
tPHL
Propagation Delay
Time High to Low
Level Output
Data
to
Q
18 27
tPLH
Propagation Delay
Enable
Time Low to High
to
30 38
www.DataSheet4U.com
Level Output
Q
tPHL
Propagation Delay
Enable
Time High to Low
to
30 36
Level Output
Q
tPZH
Output Enable
Time to High
Level Output
Output
Control
to Any Q
28
36
tPZL Output Enable
Time to Low
Level Output
Output
Control
to Any Q
36
50
tPHZ
Output Disable
Time from High
Level Output (Note 3)
Output
Control
to Any Q
20
tPLZ Output Disable
Time from Low
Output
Control
Level Output (Note 3)
to Any Q
25
Note 1 All typicals are at VCC e 5V TA e 25 C
Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second
Note 3 CL e 5 pF
Recommended Operating Conditions
Symbol
Parameter
DM54LS374
Min Nom Max
VCC Supply Voltage
45 5 55
VIH High Level Input Voltage
2
VIL Low Level Input Voltage
07
IOH High Level Output Current
b1
IOL Low Level Output Current
12
tW Pulse Width
(Note 4)
Clock High
Clock Low
15
15
tSU Data Setup Time (Notes 1 4)
20u
tH Data Hold Time (Notes 1 4)
1u
TA Free Air Operating Temperature
b55
uNote 1 The symbol ( ) indicates the rising edge of the clock pulse is used for reference
Note 4 TA e 25 C and VCC e 5V
125
DM74LS374
Min Nom Max
4 75 5 5 25
2
08
b2 6
24
15
15
20u
1u
0 70
Units
ns
ns
ns
ns
ns
ns
ns
ns
Units
V
V
V
mA
mA
ns
ns
ns
C
4

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54LS374 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters) (Continued)
www.DataSheet4U.com
20-Lead Wide Small Outline Molded Package (M)
Order Number DM74LS373WM or DM74LS374WM
NS Package Number M20B
20-Lead Molded Dual-In-Line Package (N)
Order Number DM74LS373N and DM74LS374N
NS Package Number N20A
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일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

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54LS374

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