U87C196MC PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 U87C196MC
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U87C196MC 데이터시트, 핀배열, 회로
87C196MC 16 Kbytes of On-Chip OTPROM
87C196MC ROM 16 Kbytes of On-Chip Factory-Programmed OTPROM
80C196MC ROMless
Y High-Performance CHMOS 16-Bit CPU
Y 16 Kbytes of On-Chip OTPROM
Factory-Programmed OTPROM
Y 488 bytes of On-Chip Register RAM
Y Register to Register Architecture
Up to 53 I O Lines
Y Peripheral Transaction Server (PTS)
with 11 Prioritized Sources
Y Event Processor Array (EPA)
4 High Speed Capture Compare
4 High Speed Compare Modules
Y Extended Temperature Standard
Y Two 16-Bit Timers with Quadrature
Decoder Input
Y 3-Phase Complementary Waveform
Y 13 Channel 8 10-Bit A D with Sample
Hold with Zero Offset Adjustment H W
Y 14 Prioritized Interrupt Sources
Y Flexible 8- 16-Bit External Bus
Y 1 75 ms 16 x 16 Multiply
Y 3 ms 32 16 Divide
Y Idle and Power Down Modes
The 8XC196MC is a 16-bit microcontroller designed primarily to control 3 phase AC induction and DC brush-
less motors The 8XC196MC is based on Intel’s MCS 96 16-bit microcontroller architecture and is manufac-
tured with Intel’s CHMOS process
The 8XC196MC has a three phase waveform generator specifically designed for use in ‘‘Inverter’’ motor
control applications This peripheral allows for pulse width modulation three phase sine wave generation with
minimal CPU intervention It generates 3 complementary non-overlapping PWM pulses with resolutions of
0 125 ms (edge trigger) or 0 250 ms (centered)
The 8XC196MC has 16 Kbytes on-chip OTPROM ROM and 488 bytes of on-chip RAM It is available in three
packages PLCC (84-L) SDIP (64-L) and EIAJ QFP (80-L)
Note that the 64-L SDIP package does not include P1 4 P2 7 P5 1 and the CLKOUT pins
Operational characteristics are guaranteed over the temperature range of b40 C to a85 C
The 87C196MC contains 16 Kbytes on-chip OTPROM The 83C196MC contains 16 Kbytes on-chip ROM All
references to the 80C196MC also refers to the 83C196MC and 87C196MC unless noted
OTPROM (One Time Programmable Read Only Memory) is the same as EPROM but it comes in an unwindowed package
and cannot be erased It is user programmable
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
April 1994
Order Number 270946-005

U87C196MC pdf, 반도체, 판매, 대치품
270946 – 2
The pin sequence is correct
The 64-Lead SDIP package does not include the following pins P1 4 ACH12 P2 7 COMPARE3 P5 1 INST
Figure 2 64-Lead Shrink DIP (SDIP) Package


U87C196MC 전자부품, 판매, 대치품
PIN DESCRIPTIONS (Alphabetically Ordered)
ACH0 – ACH12
(P0 0–P0 7 P1 0–P1 4)
ALE ADV(P5 0) BHE WRH (P5 5)
(P2 0–P2 3)
(P2 4–P2 7)
INST (P5 1)
Analog inputs to the on-chip A D converter ACH0 – 7 share the input pins
with P0 0–7 and ACH8 – 12 share pins with P1 0 – 4 If the A D is not used
the port pins can be used as standard input ports
Reference ground for the A D converter Must be held at nominally the
same potential as VSS
Address Latch Enable or Address Valid output as selected by CCR Both
options allow a latch to demultiplex the address data bus on the signal’s
falling edge When the pin is ADV it goes inactive (high) at the end of the
bus cycle ALE ADV is active only during external memory accesses Can be
used as standard I O when not used as ALE ADV
Byte High Enable or Write High output as selected by the CCR BHE will go
low for external writes to the high byte of the data bus WRH will go low for
external writes where an odd byte is being written BHE WRH is activated
only during external memory writes
Input for bus width selection If CCR bits 1 and 2 e 1 this pin dynamically
controls the bus width of the bus cycle in progress If BUSWIDTH is low an
8-bit cycle occurs If it is high a 16-bit cycle occurs This pin can be used as
standard I O when not used as BUSWIDTH
The EPA Capture Compare pins These pins share P2 0 – P2 3 If not used
for the EPA they can be configured as standard I O pins
Output of the internal clock generator The frequency is of the oscillator
frequency It has a 50% duty cycle
The EPA Compare pins These pins share P2 4 – P2 7 If not used for the
EPA they can be configured as standard I O pins
External Access enable pin EA e 0 causes all memory accesses to be
external to the chip EA e 1 causes memory accesses from location 2000H
to 5FFFH to be from the on-chip OTPROM QROM EA e 12 5V causes
execution to begin in the programming mode EA is latched at reset
A programmable input on this pin causes a maskable interrupt vector
through memory location 203CH The input may be selected to be a
positive negative edge or a high low level using WG PROTECT (1FCEH)
INST is high during the instruction fetch from the external memory and
throughout the bus cycle It is low otherwise This pin can be configured as
standard I O if not used as INST
A positive transition on this pin causes a non-maskable interrupt which
vectors to memory location 203EH If not used it should be tied to VSS May
be used by Intel Evaluation boards
8-bit high impedance input-only port Also used as A D converter inputs
Port0 pins should not be left floating These pins also used to select
programming modes in the OTPROM devices
5-bit high impedance input-only port P1 0 – P1 4 are also used as A D
converter inputs In addition P1 2 and P1 3 can be used as Timer 1 clock
input and direction select respectively
8-bit bidirectional I O port All of the Port2 pins are shared with the EPA I O
pins (CAPCOMP0 – 3 and COMPARE0 – 3)
8-bit bidirectional I O ports with open drain outputs These pins are shared
with the multiplexed address data bus which uses strong internal pullups
8-bit bidirectional I O port 7 of the pins are shared with bus control signals
(ALE INST WR RD BHE READY BUSWIDTH) Can be used as standard


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