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AKD5700 데이터시트 PDF




Asahi Kasei Microsystems에서 제조한 전자 부품 AKD5700은 전자 산업 및 응용 분야에서
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부품번호 AKD5700 기능
기능 16-Bit Mono ADC
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AKD5700 데이터시트, 핀배열, 회로
ASAHI KASEI
[AK5700]
AK5700
16-Bit ΔΣ Mono ADC with PLL & MIC-AMP
GENERAL DESCRIPTION
The AK5700 features a 16-bit mono ADC. Input circuits include a Microphone-Amplifier and an ALC (Auto
Level Control) circuit that is suitable for portable application with recording function. On-chip PLL supports
base-band clock of mobile phone, therefore it is easy to connect with DSP. The AK5700 is available in a
24pin QFN, utilizing less board space than competitive offerings.
www.DataSheet4U.com
FEATURES
1. Resolution: 16bits
2. Recording Function
- Input Selector
- Full-differential or Single-ended Input
- MIC Amplifier (+30dB/+15dB or 0dB)
- Input Voltage: 1.8Vpp@AVDD=3.0V (= 0.6 x AVDD)
- ADC Performance: S/(N+D): 78dB, DR, S/N: 89dB@MGAIN=0dB
S/(N+D): 77dB, DR, S/N: 87dB@MGAIN=+15dB
S/(N+D): 72dB, DR, S/N: 77dB@MGAIN=+30dB
- Digital HPF for DC-offset cancellation (fc=3.4Hz@fs=44.1kHz)
- Digital ALC (Automatic Level Control)
(+36dB ∼ −54dB, 0.375dB Step, Mute)
3. Sampling Rate:
- PLL Slave Mode (EXLRCK pin): 7.35kHz 48kHz
- PLL Slave Mode (EXBCLK pin): 7.35kHz 48kHz
- PLL Slave Mode (MCKI pin):
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
- PLL Master Mode:
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
- EXT Slave Mode:
7.35kHz 48kHz (256fs), 7.35kHz 26kHz (512fs), 7.35kHz 13kHz (1024fs)
4. PLL Input Clock:
- MCKI pin:
27MHz, 26MHz, 24MHz, 19.2MHz, 13.5MHz, 13MHz, 12.288MHz, 12MHz,
11.2896MHz
- EXLRCK pin: 1fs
- EXBCLK pin: 32fs/64fs
5. Master/Slave mode
6. Audio Interface Format: MSB First, 2’s complement
- DSP Mode, 16bit MSB justified, I2S
7. μP I/F: 3-wire Serial
8. Power Supply:
- AVDD: 2.4 3.6V
- DVDD: 1.6 3.6V
9. Power Supply Current: 6mA
10. Ta = 30 85°C
11. Package: 24pin QFN (4mm x 4mm)
12. Pin and Register compatible with AK5701 Stereo Version
MS0569-E-01
-1-
2006/12




AKD5700 pdf, 반도체, 판매, 대치품
ASAHI KASEI
[AK5700]
PIN/FUNCTION
No. Pin Name
I/O
Function
1 VCOM
O
Common Voltage Output Pin, 0.5 x AVDD
Bias voltage of ADC inputs.
2 AVSS
- Analog Ground Pin
3 AVDD
- Analog Power Supply Pin
4 DVDD
- Digital Power Supply Pin
5 DVSS
- Digital Ground Pin
6 BCLK
O Audio Serial Data Clock Pin
7 LRCK
O Input / Output Channel Clock Pin
8 SDTO
O Audio Serial Data Output Pin
Chip Select Polarity Pin
www.DataSheet4U.com 9 CSP
I “H”: CSN pin = “H” active, C1-0 = “01”
“L”: CSN pin = “L” active, C1-0 = “10”
10 MCKO
O Master Clock Output Pin
11 EXSDTI
I External Audio Serial Data Input Pin
12 EXLRCK
I External Input / Output Channel Clock Pin
13 EXBCLK
I External Audio Serial Data Clock Pin
14 MCKI
I External Master Clock Input Pin
15 CDTI
I Control Data Input Pin
16 CCLK
I Control Data Clock Pin (Internal Pull-down at CSP pin = “H”)
17 CSN
I Chip Select Pin
18 PDN
I
Power-Down Mode Pin
“H”: Power-up, “L”: Power-down, reset and initializes the control register.
19 MPWR
20 TEST
O MIC Power Supply Pin
-
Test Pin
This pin should be left floating.
21 AIN2
I Analog Input 2 Pin
22 AIN
I Negative Input Pin
23
AIN1
AIN+
I Analog Input 1 Pin
I Positive Input Pin
(MDIF1 bit = “0”: Single-ended Input)
(MDIF1 bit = “1”: Full-differential Input)
24 VCOC
O
Output Pin for Loop Filter of PLL Circuit
This pin should be connected to AVSS with one resistor and capacitor in series.
Note 1. All input pins except analog input pins (AIN1, AIN1, AIN2) should not be left floating.
„ Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification
Analog
Digital
Pin Name
MPWR, VCOC, AIN1/AIN+, AIN, AIN2
BCLK, LRCK, SDTO, MCKO
MCKI, EXBCLK, EXLRCK, EXSDTI
Setting
These pins should be open.
These pins should be open.
These pins should be connected to DVSS.
MS0569-E-01
-4-
2006/12

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AKD5700 전자부품, 판매, 대치품
ASAHI KASEI
[AK5700]
FILTER CHARACTERISTICS
(Ta=25°C; AVDD=2.4 3.6V; DVDD=1.6 3.6V; fs=44.1kHz)
Parameter
Symbol
min
ADC Digital Filter (Decimation LPF):
Passband (Note 14)
±0.1dB
1.0dB
Stopband (Note 14)
3.0dB
Passband Ripple
Stopband Attenuation
Group Delay (Note 15)
Group Delay Distortion
ADC Digital Filter (HPF): HPF1-0 bits = “00”
www.DataSheet4U.comFrequency Response (Note 14) 3.0dB
0.5dB
0.1dB
PB
SB
PR
SA
GD
ΔGD
FR
0
-
-
25.7
-
65
-
-
-
-
-
typ
-
20.0
21.1
-
-
-
18
0
3.4
10
22
max Units
17.4 kHz
- kHz
- kHz
- kHz
±0.1 dB
- dB
- 1/fs
- μs
- Hz
- Hz
- Hz
Note 14. The passband and stopband frequencies scale with fs (system sampling rate).
For example, PB=0.454*fs (@1.0dB). Each response refers to that of 1kHz.
Note 15. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the
16-bit data from the input register to the output register of the ADC. This time includes the group delay of the
HPF.
DC CHARACTERISTICS
(Ta=25°C; AVDD=2.4 3.6V; DVDD=1.6 3.6V)
Parameter
High-Level Input Voltage
Except CSP pin; 2.2VDVDD 3.6V
Except CSP pin; 1.6VDVDD <2.2V
CSP pin
Low-Level Input Voltage
Except CSP pin; 2.2VDVDD 3.6V
Except CSP pin; 1.6VDVDD <2.2V
CSP pin
High-Level Output Voltage (Iout= 200μA)
Low-Level Output Voltage (Iout= 200μA)
Input Leakage Current (Note 16)
Symbol
VIH
VIH
VIH
VIL
VIL
VIL
VOH
VOL
Iin
min
70%DVDD
80%DVDD
90%DVDD
-
-
-
DVDD0.2
-
-
typ
-
-
-
-
-
-
-
-
-
Note 16. When CSP pin is “H”, CCLK pin has internal pull-down device, normally 100kΩ.
max
-
-
-
30%DVDD
20%DVDD
10%DVDD
-
0.2
±10
Units
V
V
V
V
V
V
V
V
μA
MS0569-E-01
-7-
2006/12

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