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PDF AKD5702 Data sheet ( Hoja de datos )

Número de pieza AKD5702
Descripción 4-Channel ADC
Fabricantes Asahi Kasei Microsystems　
Logotipo Asahi Kasei Microsystems Logotipo



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No Preview Available ! AKD5702 Hoja de datos, Descripción, Manual

[AK5702]
AK5702
4-Channel ADC with PLL & MIC-AMP
GENERAL DESCRIPTION
The AK5702 features a 4-channel ADC. Input circuits include a Microphone-Amplifier with programmable
gain and an ALC (Auto Level Control) circuit, making it ideal for consumer microphone array applications.
On-chip PLL and TDM audio format makes it easy to connect with DSP. The AK5702 has a software
compatibility with stereo version, AK5701.
FEATURES
www.DataSheet4U.com 1. Recording Function
- 4-Channel ADC
- 3:1 Stereo Input Selector
- Full-differential or Single-ended Input
- MIC Amplifier (+36dB/+30dB/+15dB/0dB)
- Input Voltage: 1.8Vpp@AVDD=3.0V (= 0.6 x AVDD)
- ADC Performance:
S/(N+D): 83dB, DR, S/N: 89dB@MGAIN=0dB
S/(N+D): 83dB, DR, S/N: 87dB@MGAIN=+15dB
- Digital HPF for DC-offset cancellation (fc=3.4Hz@fs=44.1kHz)
- Digital ALC
- Input Digital Volume (+36dB ∼ −54dB, 0.375dB Step, Mute)
2. Sampling Rate:
- PLL Slave Mode (LRCK pin): 7.35kHz ∼ 48kHz
- PLL Slave Mode (BCLK pin): 7.35kHz ∼ 48kHz
- PLL Slave Mode (MCKI pin):
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
- PLL Master Mode:
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
- EXT Slave Mode:
7.35kHz ∼ 48kHz (256fs), 7.35kHz ∼ 26kHz (512fs),
7.35kHz ∼ 13kHz (1024fs)
3. PLL Input Clock:
- MCKI pin:
27MHz, 26MHz, 24MHz, 19.2MHz, 13.5MHz, 13MHz, 12.288MHz, 12MHz,
11.2896MHz
- LRCK pin: 1fs
- BCLK pin: 32fs/64fs
4. Master/Slave mode
5. Audio Interface Format: MSB First, 2’s complement
- DSP Mode, 16bit MSB justified, I2S
- Cascade TDM interface
6. μP I/F: 3-wire Serial or I2C Bus (Ver 1.0, 400kHz Mode)
7. Power Supply:
- AVDD: 2.4 ∼ 3.6V
- DVDD: 1.6 ∼ 3.6V (Stereo Mode)
- DVDD: 2.0 ∼ 3.6V (TDM128 Mode, 16bit x 8ch)
- DVDD: 2.7 ∼ 3.6V (TDM256 Mode, 32bit x 8ch)
8. Power Supply Current: 13 mA (EXT Slave Mode)
9. Ta = −30 ∼ 85°C
10. Package: 32pin QFN (5mm x 5mm)
11. Register Compatible with AK5701
MS0623-E-00
-1-
2007/06

1 page




AKD5702 pdf
[AK5702]
■ Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification
Analog
Digital
Pin Name
MPWRA, MPWRB, VCOC, LIN1/LINA+,
RIN1/LINA−, LIN2/RINA−, RIN2/RINA+,
LIN3/LINB+, RIN3/LINB−, LIN4/RINB−,
RIN4/RINB+, RIN5, LIN5
SDTOA, SDTOB, MCKO
MCKI, TDMIN
Setting
These pins should be open.
These pins should be open.
This pin should be connected to VSS2.
www.DataSheet4U.com
ABSOLUTE MAXIMUM RATINGS
(VSS1, VSS2=0V; Note 2)
Parameter
Symbol
min
Power Supplies: Analog
AVDD
−0.3
Digital
DVDD
−0.3
Input Current, Any Pin Except Supplies
IIN -
Analog Input Voltage (Note 3)
VINA
−0.3
Digital Input Voltage (Note 4)
VIND
−0.3
Ambient Temperature (powered applied)
Ta −30
Storage Temperature
Tstg −65
max
4.6
4.6
±10
AVDD+0.3
DVDD+0.3
85
150
Units
V
V
mA
V
V
°C
°C
Note 2. All voltages with respect to ground. VSS1 and VSS2 must be connected to the same analog ground plane.
Note 3. LIN1/LINA+, RIN1/LINA−, LIN2/RINA−, RIN2/RINA+, LIN3/LINB+, RIN3/LINB−, LIN4/RINB−,
RIN4/RINB+, LIN5/RIN5 pins
Note 4. PDN, CSN/CAD1, CCLK/SCL, CDTI/SDA, MCKI, LRCK, BCLK, TEST, TDMIN, I2C, CAD0 pins
Pull-up resistors at SDA and SCL pins should be connected to (DVDD+0.3) V or less voltage.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1, VSS2=0V; Note 2)
Parameter
Symbol min typ
Power Supplies Analog
AVDD
2.4 3.0
(Note 5) Digital (Stereo mode)
DVDD
1.6 3.0
(TDM128 mode)
2.0 3.0
(TDM256 mode)
2.7 3.0
max
3.6
AVDD
AVDD
AVDD
Units
V
V
V
V
Note 2. All voltages with respect to ground. VSS1 and VSS2 must be connected to the same analog ground plane.
Note 5. The power-up sequence between AVDD and DVDD is not critical. When only AVDD is powered OFF (Hi_Z or
L), it should be done after the PDN pin = “L” or all power management bits (PMADAL, PMADAR, PMADBL,
PMADBR, PMVCM, PMPLL, PMMPA, PMMPB) = “0”. DVDD should not be powerd OFF while AVDD is
powered ON.
WARNING: AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0623-E-00
-5-
2007/06

5 Page





AKD5702 arduino
[AK5702]
Parameter
Symbol
Audio Interface Timing (Stereo DSP Mode)
Master Mode
LRCK “↑” to BCLK “↑” (Note 18)
LRCK “↑” to BCLK “↓” (Note 19)
BCLK “↑” to SDTO (BCKP bit = “0”)
BCLK “↓” to SDTO (BCKP bit = “1”)
tDBF
tDBF
tBSD
tBSD
Slave Mode
LRCK “↑” to BCLK “↑” (Note 18)
tLRB
LRCK “↑” to BCLK “↓” (Note 19)
BCLK “↑” to LRCK “↑” (Note 18)
www.DataSheet4U.comBCLK “↓” to LRCK “↑” (Note 19)
BCLK “↑” to SDTO (BCKP bit = “0”)
BCLK “↓” to SDTO (BCKP bit = “1”)
Audio Interface Timing (Left justified & I2S)
tLRB
tBLR
tBLR
tBSD
tBSD
Master Mode
BCLK “↓” to LRCK Edge (Note 20)
tMBLR
LRCK Edge to SDTO (MSB)
(Except I2S mode)
tLRD
BCLK “↓” to SDTO
tBSD
Slave Mode
LRCK Edge to BCLK “↑” (Note 20)
BCLK “↑” to LRCK Edge (Note 20)
LRCK Edge to SDTO (MSB)
(Except I2S mode)
tLRB
tBLR
tLRD
BCLK “↓” to SDTO
tBSD
Audio Interface Timing (TDM128 Mode)
Master Mode
BCLK “↓” to LRCK
BCLK “↓” to SDTOB (Note 21)
TDMIN Hold Time
tMBLR
tBSD
tTDMH
TDMIN Setup Time
tTDMS
Slave Mode
LRCK Edge to BCLK “↑” (Note 20)
BCLK “↑” to LRCK Edge (Note 20)
tLRB
tBLR
BCLK “↓” to SDTOB (Note 21)
TDMIN Hold Time
tBSD
tTDMH
TDMIN Setup Time
tTDMS
Audio Interface Timing (TDM256 Mode)
Master Mode
BCLK “↓” to LRCK
tMBLR
BCLK “↓” to SDTOB (Note 21)
TDMIN Hold Time
tBSD
tTDMH
TDMIN Setup Time
tTDMS
Slave Mode
LRCK Edge to BCLK “↑” (Note 20)
BCLK “↑” to LRCK Edge (Note 20)
BCLK “↓” to SDTOB (Note 21)
TDMIN Hold Time
tLRB
tBLR
tBSD
tTDMH
TDMIN Setup Time
tTDMS
min
0.5 x tBCK − 40
0.5 x tBCK − 40
−70
−70
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
-
-
−40
−70
−70
50
50
-
-
-24
-40
20
20
40
40
-
20
20
-12
-20
10
10
20
20
-
10
10
typ
0.5 x tBCK
0.5 x tBCK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
max
0.5 x tBCK + 40
0.5 x tBCK + 40
70
70
-
-
-
-
80
80
40
70
70
-
-
80
80
24
40
-
-
-
-
40
-
-
12
20
-
-
-
-
20
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 18. MSBS, BCKP bits = “00” or “11”
Note 19. MSBS, BCKP bits = “01” or “10”
Note 20. BCLK rising edge must not occur at the same time as LRCK edge.
Note 21. SDTOA is fixed to “L”.
MS0623-E-00
- 11 -
2007/06

11 Page







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