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EK7309 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 EK7309
기능 256-Output Gate Driver /COF/2 Level
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EK7309 데이터시트, 핀배열, 회로
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CONFIDENTIAL




EK7309 pdf, 반도체, 판매, 대치품
EUREKA
EK7309
TFT Gate Driver (256 Outputs)
1. GENERAL DESCRIPTION
EK7309 is a TFT LCD gate driver with 256 outputs
for XGA/SXGA display systems. The logic and
control portion is implemented in standard CMOS
circuits while the output drivers use high voltage
CMOS design. The low voltage part includes a 256-
stage bidirectional shift register with right and left
shift I/O for cascading. The output of the shift register
is then level translated to drive the high voltage
www.DataSheeto4uUt.pcoumt buffer. There are four supply voltages for
EK7309. VDD/VSS are the supply voltages for logic
interfaces. Typically VDD is at 3.3V while VSS is 0V.
VGG and VEE are the supply voltages for the
output driver. VEE is the most negative supply
voltage for the internal substrate of EK7309.
EK7309 allows three output enable controls (OE1-
3) and one global enable signal (XON).
2. FEATURES
• 256 gate drive outputs
• Bidirectional shift control and cascadable
• Output enable and global on control
• Maximum shift clock frequency up to 100KHz
• 3.3V CMOS logic I/O
• High voltage output drive
• Operating supply range
Logic (VDD-VSS: 3.3V)
Output Drive (VGG -VEE: 40V)
• TCP package
3. BLOCK DIAGRAM
VGG
VEE
VDD
VSS
XON
DIO1
X1 X256
High voltage output and level shifters
CONFIDENTIALOE3
Low voltage logic and IO
OE2
OE1
DIO2
SCLK
RL
May 2003
-01- Preliminary Rev 0.2

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EK7309 전자부품, 판매, 대치품
EUREKA
EK7309
6. FUNCTIONAL DESCRIPTION
6.1 When RL is “HIGH” and a start pulse inputs the DIO1 pin, this pulse is shifted right by the shift control register
at the rising edge of SCLK. While the output of the shift control register is “HIGH”, the Xn [n=1, 2, 3,..., 256]
is pulled to VGG. If the output of the shift control register is “LOW”, Xn [n=1, 2, 3,..., 256] is pushed to
VEE; DIO2 is pulled to high at the falling edge of the 256th clock of SCLK and is pushed to low at the falling
edge of the 257th clock of SCLK. Please refer to operating waveform (1).
6.2 When RL is “LOW” and a start pulse inputs the DIO2 pin, this pulse is shifted left by the shift control register at
the rising edge of SCLK. While the output of the shift control register is “HIGH”, the Xn [n=256, 255, 254,...,
1] is pulled to VGG. If the output of the shift control register is “LOW”, Xn [n=256, 255, 254,..., 1] is
www.DataSheet4U.cpomushed to VEE; DIO1 is pulled to high at the falling edge of the 256th clock of SCLK and is pushed to low at
the falling edge of the 257th clock of SCLK. Please refer to operating waveform (2).
6.3 OE1, OE2, and OE3 can disable Xn [n=1, 2, 3,..., 256]. They are asynchronous to SCLK.
Xn [n=1, 4, 7,..., 253, 256] is pushed to VEE when OE1 is “HIGH”.
Xn [n=2, 5, 8,..., 251, 254] is pushed to VEE when OE2 is “HIGH”.
Xn [n=3, 6, 9,..., 252, 255] is pushed to VEE when OE3 is “HIGH”.
Please refer to operating waveform (1) and (2).
6.4 The global on control XON can enable Xn [n=1, 2, 3,..., 256]. It is asynchronous to SCLK. Whenever XON
is “LOW”, all outputs of EK7309 are pulled to VGG at the same time. Please refer to operating waveform (3).
CONFIDENTIAL
May 2003
-04- Preliminary Rev 0.2

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전력 반도체 판매 ( IGBT, TR 모듈, SCR, 다이오드 모듈 )

휴대전화 : 010-3582-2743


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