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CYV15G0203TB 데이터시트 PDF




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부품번호 CYV15G0203TB 기능
기능 Independent Clock Dual HOTLink II Serializer
제조업체 Cypress Semiconductor
로고 Cypress Semiconductor 로고


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CYV15G0203TB 데이터시트, 핀배열, 회로
PRELIMINARY
CYV15G0203TB
Independent Clock Dual HOTLink II™ Serializer
Features
• Dual channel video serializer
— 195- to 1500-Mbps serial data signaling rate
— Simultaneous operation at different signaling rates
• Second-generation HOTLink® technology
• Compliant to SMPTE 292M and SMPTE 259M video
www.DataSheet4Us.tcaonmdards
• Supports half-rate and full-rate clocking
• Internal phase-locked loops (PLLs) with no external
PLL components
• Redundant differential PECL-compatible serial outputs
per channel
— No external bias resistors required
— Signaling-rate controlled edge-rates
— Internal source termination
• Synchronous LVTTL parallel interface
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Low-power 1.4W @ 3.3V typical
• Single 3.3V supply
• Thermally enhanced BGA
• 0.25µ BiCMOS technology
Functional Description
The CYV15G0203TB Independent Clock Dual HOTLink II™
Serializer is a point-to-point or point-to-multipoint communica-
tions building block enabling transfer of data over a variety of
high-speed serial links including SMPTE 292M and SMPTE
259M video applications. It supports signaling rates in the
range of 195 to 1500 Mbps per serial link. The two channels
are independent and can simultaneously operate at different
rates. Each channel accepts 10-bit parallel characters in an
Input Register and converts them to serial data. Figure 1 illus-
trates typical connections between independent video co-
processors and corresponding CYV15G0203TB Serializer
and CYV15G0204RB Reclocking Deserializer chips.
The CYV15G0203TB satisfies the SMPTE-259M and SMPTE-
292M compliance as per SMPTE EG34-1999 Pathological
Test Requirements.
As a second-generation HOTLink device, the
CYV15G0203TB extends the HOTLink family with enhanced
levels of integration and faster data rates, while maintaining
serial-link compatibility (data, and BIST) with other HOTLink
devices. Each channel of the CYV15G0203TB Dual HOTLink
II device accepts scrambled 10-bit transmission characters.
These characters are serialized and output from dual Positive
ECL (PECL) compatible differential transmission-line drivers
at a bit-rate of either 10- or 20-times the input reference clock
for that channel.
Each channel contains an independent BIST pattern
generator. This BIST hardware allows at-speed testing of the
high-speed serial data paths in each transmit section of this
device, each receive section of a connected HOTLink II
device, and across the interconnecting links.
The CYV15G0203TB is ideal for SMPTE applications where
different data rates and serial interface standards are
necessary for each channel. Some applications include multi-
format routers, switchers, format converters, and cameras.
Reclocked
Output
10
Independent
Channel
CYV15G0203TB
Serializer
10
Serial Links
Independent
Channel
CYV15G0204RB
Reclocking Deserializer
10
10
Reclocked
Output
Figure 1. HOTLink II™ System Connections
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-02105 Rev. **
Revised July 21, 2004




CYV15G0203TB pdf, 반도체, 판매, 대치품
Pin Configuration (Top View)[1]
PRELIMINARY
CYV15G0203TB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A
NC
NC
NC
NC
VCC
NC
OUT GND GND OUT GND OUT GND GND OUT
B1– B2– A1– A2–
VCC
VCC
NC
VCC
NC
B
VCC
NC
VCC
NC
VCC
VCC
OUT GND
B1+
NC
OUT
B2+
NC
OUT GND NC
A1+
OUT
A2+
VCC
NC
NC
NC
NC
C
TDI
TMS VCC VCC VCC NC
NC GND NC
NC
DATA DATA GND
[2] [0]
NC
SPD
SELB
VCC
NC TRST GND TDO
D
www.DataSheet4U.comTCLK RESET VCC VCC VCC VCC
NC GND GND DATA DATA GND GND GND NC
[3] [1]
VCC
NC
NC SCAN TMEN3
EN2
E
VCC VCC VCC VCC
VCC VCC VCC VCC
F
NC NC VCC NC
NC NC NC NC
G
GND WREN GND GND
H
GND GND GND GND
NC NC SPD NC
SELA
GND GND GND GND
J
GND GND GND GND
NC NC NC NC
K
NC NC GND GND
NC NC NC NC
L
NC NC NC GND
NC NC NC GND
M
NC NC NC NC
NC NC NC GND
N
GND GND GND GND
GND GND GND GND
P
NC NC NC NC
GND GND GND GND
R
NC NC NC NC
VCC VCC VCC VCC
T
VCC VCC VCC VCC
VCC VCC VCC VCC
U
TX TX
DB[0] DB[1]
TX TX
DB[2] DB[9]
VCC
NC
NC
GND TX ADDR REF TX GND TX
TX
DA[9] [0] CLKB– DA[1]
DA[4] DA[8]
VCC
NC
VCC
NC
NC
V
TX TX TX NC
DB[3] DB[4] DB[8]
VCC
NC
NC
GND
NC
GND REF TX GND TX
TX
CLKB+ CLKOA
DA[3] DA[7]
VCC
NC
NC
NC
NC
W
TX TX NC
DB[5] DB[7]
NC
VCC
NC
NC
GND ADDR ADDR
[2] [1]
NC
TX GND TX
TX
ERRA
DA[2] DA[6]
VCC
NC REF NC
CLKA+
NC
Y
TX TX NC
DB[6] CLKB
NC
VCC
NC
NC
GND TX
NC
CLKOB
TX
CLKA
NC
GND TX
TX
DA[0] DA[5]
VCC
TX REF
ERRB CLKA–
NC
NC
1. NC = Do not connect.
Document #: 38-02105 Rev. **
Page 4 of 19

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CYV15G0203TB 전자부품, 판매, 대치품
PRELIMINARY
CYV15G0203TB
Pin Definitions (continued)
CYV15G0203TB Dual HOTLink II Serializer
Name
SPDSELA
SPDSELB
I/O Characteristics Signal Description
3-Level Select[4]
static control input
Serial Rate Select. The SPDSELx inputs specify the operating signaling-rate range
of each channel’s PLL.
LOW = 195 – 400 MBd
MID = 400 – 800 MBd
HIGH = 800 – 1500 MBd.
Device Configuration and Control Bus Signals
WREN
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ADDR[2:0]
LVTTL input,
asynchronous,
internal pull-up
LVTTL input
asynchronous,
internal pull-up
Control Write Enable. The WREN input writes the values of the DATA[3:0] bus into
the latch specified by the address location on the ADDR[2:0] bus.[5]
Control Addressing Bus. The ADDR[2:0] bus is the input address bus used to
configure the device. The WREN input writes the values of the DATA[3:0] bus into
the latch specified by the address location on the ADDR[2:0] bus.[5] Table 2 lists the
configuration latches within the device, and the initialization value of the latches upon
the assertion of RESET. Table 3 shows how the latches are mapped in the device.
DATA[3:0]
LVTTL input
asynchronous,
internal pull-up
Control Data Bus. The DATA[3:0] bus is the input data bus used to configure the
device. The WREN input writes the values of the DATA[3:0] bus into the latch
specified by address location on the ADDR[2:0] bus.[5 ] Table 2 lists the configuration
latches within the device, and the initialization value of the latches upon the assertion
of RESET. Table 3 shows how the latches are mapped in the device.
Internal Device Configuration Latches
TXCKSEL[A..B] Internal Latch[6]
Transmit Clock Select.
TXRATE[A..B] Internal Latch[6]
Transmit PLL Clock Rate Select.
TXBIST[A..B]
Internal Latch[6]
Transmit Bist Disabled.
OE2[A..B]
Internal Latch[6]
Differential Serial Output Driver 2 Enable.
OE1[A..B]
Internal Latch[6]
Differential Serial Output Driver 1 Enable.
PABRST[A..B] Internal Latch[6]
Transmit Clock Phase Alignment Buffer Reset.
Factory Test Modes
SCANEN2
LVTTL input,
internal pull-down
Factory Test 2. SCANEN2 input is for factory testing only. This input may be left as
a NO CONNECT, or GND only.
TMEN3
LVTTL input,
internal pull-down
Factory Test 3. TMEN3 input is for factory testing only. This input may be left as a
NO CONNECT, or GND only.
Analog I/O
OUTA1±
OUTB1±
CML Differential
Output
Primary Differential Serial Data Output. The OUTx1± PECL-compatible CML
outputs (+3.3V referenced) are capable of driving terminated transmission lines or
standard fiber-optic transmitter modules, and must be AC-coupled for PECL-
compatible connections.
OUTA2±
OUTB2±
CML Differential
Output
Secondary Differential Serial Data Output. The OUTx2± PECL-compatible CML
outputs (+3.3V referenced) are capable of driving terminated transmission lines or
standard fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible
connections.
Notes:
4. 3-Level Select inputs are used for static configuration. These are ternary inputs that make use of logic levels of LOW, MID, and HIGH. The LOW level is usually
implemented by direct connection to VSS (ground). The HIGH level is usually implemented by direct connection to VCC (power). The MID level is usually
implemented by not connecting the input (left floating), which allows it to self bias to the proper level.
5. See Device Configuration and Control Interface for detailed information on the operation of the Configuration Interface.
6. See Device Configuration and Control Interface for detailed information on the internal latches.
Document #: 38-02105 Rev. **
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부품번호상세설명 및 기능제조사
CYV15G0203TB

Independent Clock Dual HOTLink II Serializer

Cypress Semiconductor
Cypress Semiconductor

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