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PDF CYV15G0204RB Data sheet ( Hoja de datos )
| Número de pieza | CYV15G0204RB | |
| Descripción | Independent Clock Dual HOTLink IIBT Reclocking Deserializer | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CYV15G0204RB
Independent Clock Dual HOTLink II™
Reclocking Deserializer
Features
• Second-generation HOTLink® technology
• Compliant to SMPTE 292M and SMPTE 259M video
standards
• Dual-channel video reclocking deserializer
— 195- to 1500-Mbps serial data signaling rate
www.DataSheet4U—.coSmimultaneous operation at different signaling rates
• Supports reception of either 1.485 or 1.485/1.001 Gbps data
rate with the same training clock
• Supports half-rate and full-rate clocking
• Internal phase-locked loops (PLLs) with no external PLL
components
• Selectable differential PECL-compatible serial inputs
— Internal DC-restoration
• Synchronous LVTTL parallel interface
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Link Quality Indicator
— Analog signal detect
— Digital signal detect
• Low-power 2W @ 3.3V typical
• Single 3.3V supply
• Thermally enhanced BGA
• Pb-Free package option available
• 0.25μ BiCMOS technology
Functional Description
The CYV15G0204RB Independent Clock Dual HOTLink II™
Deserializing Reclocker is a point-to-point or point-to-multi-
point communications building block enabling transfer of data
over a variety of high-speed serial links including SMPTE 292
and SMPTE 259 video applications. It supports signaling rates
in the range of 195 to 1500 Mbps per serial link. The two
channels are independent and can simultaneously operate at
different rates. Each receive channel accepts serial data and
converts it to 10-bit parallel characters and presents these
characters to an Output Register. The received serial data can
also be reclocked and retransmitted through the reclocker
serial outputs. Figure 1 illustrates typical connections between
independent video co-processors and corresponding
CYV15G0204RB Reclocking Deserializer and
CYV15G0203TB Serializer chips.
The CYV15G0204RB satisfies the SMPTE-259M and
SMPTE-292M compliance as per SMPTE EG34-1999 Patho-
logical Test Requirements.
As a second-generation HOTLink device, the
CYV15G0204RB extends the HOTLink family with
enhanced levels of integration and faster data rates,
while maintaining serial-link compatibility (data and BIST)
with other HOTLink devices.
Each channel of the CYV15G0204RB Dual HOTLink II device
accepts a serial bit-stream from one of two selectable
PECL-compatible differential line receivers, and using a
completely integrated Clock and Data Recovery PLL, recovers
the timing information necessary for data reconstruction. The
recovered bit-stream is reclocked and retransmitted through
the reclocker serial outputs. Also, the recovered serial data is
deserialized and presented to the destination host system.
Each channel contains an independent BIST pattern checker.
This BIST hardware allows at-speed testing of the high-speed
serial data paths in each receive section of this device, each
transmit section of a connected HOTLink II device, and across
the interconnecting links.
The CYV15G0204RB is ideal for SMPTE applications where
different data rates and serial interface standards are
necessary for each channel. Some applications include
multi-format routers, switchers, format converters, SDI
monitors, and camera control units.
Figure 1. HOTLink II™ System Connections
Reclocked
Output
10
Independent
Channel
CYV15G0203TB
Serializer
10
Serial Links
Independent
Channel
CYV15G0204RB
Reclocking Deserializer
10
10
Reclocked
Output
Cypress Semiconductor Corporation
Document #: 38-02103 Rev. *C
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised May 2, 2007
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1 page  
CYV15G0204RB
Pin Configuration (Top View)[1]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A
NC NC NC NC VCC
B
VCC NC VCC NC VCC
C
TDI TMS VCC VCC VCC
www.DataSheet4UD.comTCLK RESET INSELB INSELA VCC
E
VCC VCC VCC VCC
IN ROUT GND IN ROUT IN ROUT GND IN ROUT
B1– B1–
B2– B2– A1– A1–
A2– A2–
IN ROUT GND IN ROUT IN ROUT GND IN ROUT
B1+ B1+
B2+ B2+ A1+ A1+
A2+ A2+
ULCB NC GND DATA DATA DATA DATA GND NC SPD
[6] [4] [2] [0]
SELB
ULCA NC GND DATA DATA DATA GND GND GND NC
[5] [3] [1]
VCC
VCC
VCC
VCC
VCC NC VCC NC
NC NC NC NC
LDTD TRST GND TDO
EN
NC
VCC
SCAN TMEN3
EN2
VCC VCC VCC VCC
F
NC NC VCC VCC
VCC NC NC NC
G
GND WREN GND GND
H
GND GND GND GND
NC NC SPD NC
SELA
GND GND GND GND
J
GND GND GND GND
NC NC NC NC
K
NC NC GND GND
NC NC NC NC
L
NC NC NC GND
NC NC NC GND
M
NC NC NC NC
NC NC NC GND
N
GND GND GND GND
GND GND GND GND
P
NC NC NC NC
GND GND GND GND
R
NC NC NC NC
VCC VCC VCC VCC
T
VCC VCC VCC VCC
VCC VCC VCC VCC
U
VCC
VCC
VCC
VCC
VCC
RX
DB[4]
RX
DB[3]
GND GND ADDR TRG GND GND GND
[0] CLKB–
VCC
VCC
RX
DA[4]
VCC
BIST RX
STA DA[0]
V
VCC
VCC
VCC
RX
DB[8]
VCC
RX
DB[5]
RX
DB[1]
GND
BIST
STB
GND TRG RE GND GND
CLKB+ CLKOA
VCC
VCC
RX RX RX RX
DA[9] DA[5] DA[2] DA[1]
W
VCC
VCC
LFIB
RX
CLKB–
VCC
RX
DB[6]
RX
DB[0]
GND ADDR ADDR RX
RE GND GND
[2] [1] CLKA+ PDOA
VCC
VCC
LFIA TRG RX
RX
CLKA+ DA[6] DA[3]
Y
VCC
VCC
RX
DB[9]
RX
CLKB+
VCC
RX RX GND RE NC
DB[7] DB[2]
CLKOB
GND RX GND GND
CLKA–
VCC
VCC
RE TRG RX
PDOB CLKA– DA[8]
RX
DA[7]
Note
1. NC = Do not connect.
Document #: 38-02103 Rev. *C
Page 5 of 24
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5 Page 
CYV15G0204RB
During the time that the Range Control forces the RXPLL VCO
to track TRGCLKx±, the LFIx output is asserted LOW. After a
valid serial data stream is applied, it may take up to one
RANGE CONTROL SAMPLING PERIOD before the PLL
locks to the input data stream, after which LFIx will be HIGH.
The operating serial signaling-rate and allowable range of
TRGCLK± frequencies are listed in Table 2.
Table 2. Operating Speed Settings
SPDSELx TRGRATEx
www.DataSheet4U.coLmOW
MID (Open)
HIGH
1
0
1
0
1
0
TRGCLKx±
Frequency
(MHz)
reserved
19.5–40
20–40
40–80
40–75
80–150
Signaling
Rate (Mbps)
195–400
400–800
800–1500
Receive Channel Enabled
The CYV15G0204RB contains two receive channels that can
be independently enabled and disabled. Each channel can be
enabled or disabled separately through the RXPLLPDx input
latch as controlled by the device configuration interface. When
the RXPLLPDx latch = 0, the associated PLL and analog
circuitry of the channel is disabled. Any disabled channel
indicates a constant link fault condition on the LFIx output.
When RXPLLPDx = 1, the associated PLL and receive
channel is enabled to receive a serial stream.
Note. When a disabled receive channel is reenabled, the
status of the associated LFIx output and data on the parallel
outputs for the associated channel may be indeterminate for
up to 2 ms.
Clock/Data Recovery
The extraction of a bit-rate clock and recovery of bits from each
received serial stream is performed by a separate CDR block
within each receive channel. The clock extraction function is
performed by an integrated PLL that tracks the frequency of
the transitions in the incoming bit stream and align the phase
of the internal bit-rate clock to the transitions in the selected
serial data stream.
Each CDR accepts a character-rate (bit-rate ÷ 10) or
half-character-rate (bit-rate ÷ 20) training clock from the
associated TRGCLKx± input. This TRGCLKx± input is used to
• ensure that the VCO (within the CDR) is operating at the
correct frequency (rather than a harmonic of the bit-rate)
• reduce PLL acquisition time
• limit unlocked frequency excursions of the CDR VCO when
there is no input data present at the selected Serial Line
Receiver.
Regardless of the type of signal present, the CDR attempts to
recover a data stream from it. If the signalling rate of the
recovered data stream is outside the limits set by the range
control monitors, the CDR tracks TRGCLKx± instead of the
data stream. Once the CDR output (RXCLK±) frequency
returns back close to TRGCLKx± frequency, the CDR input is
switched back to the input data stream. If no data is present at
the selected line receiver, this switching behavior may result
in brief RXCLK± frequency excursions from TRGCLKx±.
However, the validity of the input data stream is indicated by
the LFIx output. The frequency of TRGCLKx± is required to be
within ±1500ppm[21] of the frequency of the clock that drives
the reference clock input of the remote transmitter to ensure a
lock to the incoming data stream. This large ppm tolerance
allows the CDR PLL to reliably receive a 1.485 or 1.485/1.001
Gbps SMPTE HD-SDI data stream with a constant TRGCLK
frequency.
For systems using multiple or redundant connections, the LFIx
output can be used to select an alternate data stream. When
an LFIx indication is detected, external logic can toggle
selection of the associated INx1± and INx2± input through the
associated INSELx input. When a port switch takes place, it is
necessary for the receive PLL for that channel to reacquire the
new serial stream.
Reclocker
Each receive channel performs a reclocker function on the
incoming serial data. To do this, the Clock and Data Recovery
PLL first recovers the clock from the data. The data is retimed
by the recovered clock and then passed to an output register.
Also, the recovered character clock from the receive PLL is
passed to the reclocker output PLL which generates the bit
clock that is used to clock the retimed data into the output
register. This data stream is then transmitted through the
differential serial outputs.
Reclocker Serial Output Drivers
The serial output interface drivers use differential Current
Mode Logic (CML) drivers to provide source-matched drivers
for 50Ω transmission lines. These drivers accept data from the
reclocker output register in the reclocker channel. These
drivers have signal swings equivalent to that of standard PECL
drivers, and are capable of driving AC-coupled optical
modules or transmission lines.
Reclocker Output Channels Enabled
Each driver can be enabled or disabled separately via the
device configuration interface.
When a driver is disabled via the configuration interface, it is
internally powered down to reduce device power. If both
reclocker serial drivers for a channel are in this disabled state,
the associated internal reclocker logic is also powered down.
The deserialization logic and parallel outputs will remain
enabled. A device reset (RESET sampled LOW) disables all
output drivers.
Note. When the disabled reclocker function (i.e., both outputs
disabled) is re-enabled, the data on the reclocker serial
outputs may not meet all timing specifications for up to 250 μs.
Output Bus
Each receive channel presents a 10-bit data signal (and a
BIST status signal when RXBISTx[1:0] = 10).
Receive BIST Operation
Each receiver channel contains an internal pattern checker
that can be used to validate both device and link operation.
Document #: 38-02103 Rev. *C
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