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CYV15G0402DXB 데이터시트 PDF




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부품번호 CYV15G0402DXB 기능
기능 Quad HOTLink IIBT SERDES
제조업체 Cypress Semiconductor
로고 Cypress Semiconductor 로고


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CYV15G0402DXB 데이터시트, 핀배열, 회로
CYP15G0402DXB
CYV15G0402DXB
Quad HOTLink II™ SERDES
Features
• Second-generation HOTLink® technology
• Compliant to multiple standards
— Fibre Channel, Gigabit Ethernet (IEEE802.3z), ES-
CON® and DVB-ASI
— CYV15G0402DXB compliant to SMPTE 259M and
www.DataSheet4U.coSmMPTE 292M
• Quad-channel transceiver operates from 195 to 1500
Mbps serial data rate
— Aggregate throughput of 12 Gbps
• 10-bit unencoded data transport
• Selectable parity check/generate
• Four independent 10-bit channels with separate Clock
and Data Recovery for each channel
• Selectable input clocking options
• MultiFrame™ Receive Framer
— Comma or full K28.5 detect
— Single or Multi-Byte framer for byte alignment
— Low-latency option
• Synchronous LVTTL parallel interface
• Internal phase-locked loops (PLLs) with no external
PLL components
• Optional Phase Align Buffer in Transmit Path
• Differential PECL-compatible serial inputs
• Differential PECL-compatible serial outputs
Source matched for 50transmission lines
— No external resistors required
— Signaling rate controlled edge rates
• Compatible with
— Fiber-optic modules
— Copper cables
— Circuit board traces
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Per-channel Link Quality Indicator
— Analog signal detect
— Digital signal detect
• Low-power 2.5W @3.3V typical
• Single 3.3V supply
• 256-ball thermally enhanced BGA
• Pb-Free package option available
0.25µ BiCMOS technology
Functional Description
The CYP(V)15G0402DXB[1] Quad HOTLink II™ SERDES is a
point-to-point communications building block allowing the
transfer of preencoded data over high-speed serial links
(optical fiber, balanced, and unbalanced copper transmission
lines) at signaling speeds ranging from 195 to 1500 MBaud per
serial link.
Each transmit channel accepts preencoded 10-bit trans-
mission characters in an Input Register, serializes each
character, and drives it out a PECL-compatible differential line
driver. Each receive channel accepts a serial data stream at a
differential line receiver, deserializes the stream into 10-bit
characters, optionally frames these characters to the proper
10-bit character boundaries and presents these characters to
an Output register. Figure 1 illustrates typical connections
between independent systems and a CYP(V)15G0402DXB.
The CYV15G0402DXB satisfies the SMPTE-259M and
SMPTE-292M compliance as per the EG34-1999 Pathological
Test Requirements.
10
10
10
10
Serial Links
Serial Links
Independent
Channel
Transceiver
Independent
Channel
Transceiver
10
10
10
10
10
10
Serial Links
Independent
Channel
Transceiver
10
10
10
10
Serial Links
Cable or
Optical
Connections
Independent
Channel
Transceiver
10
10
Note:
Figure 1. CYP(V)15G0402DXB HOTLink II™ System Connections
1. CYV15G0402DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYP15G0402DXB refers to devices that are not compliant to SMPTE 259M
and SMPTE 292M pathological test requirements. CYP(V)15G0402DXB refers to both devices.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-02057 Rev. *G
Revised March 31, 2005




CYV15G0402DXB pdf, 반도체, 판매, 대치품
Receive Path Block Diagram
RXLE
BOE[7:0]
RX PLL Enable
Latch
Parity Control
Character-Rate Clock
SDASEL
LPENA
INA+
INA–
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TXLBA
Receive
Signal
Monitor
Clock and
Data
Recovery
PLL
RFENA
LPENB
INB+
INB–
TXLBB
RFENB
LPENC
INC+
INC–
TXLBC
RFENC
LPEND
IND+
IND–
TXLBD
RBIST[A..D]
RFEND
FRAMCHAR
RXRATE
RFMODE
Receive
Signal
Monitor
Clock and
Data
Recovery
PLL
Receive
Signal
Monitor
Clock and
Data
Recovery
PLL
Receive
Signal
Monitor
Clock and
Data
Recovery
PLL
Document #: 38-02057 Rev. *G
CYP15G0402DXB
CYV15G0402DXB
JTAG
Boundary
Scan
Controller
= Internal Signal
TRSTZ
TMS
TCLK
TDI
TDO
LFIA
RXDA[0..9]
RXOPA
COMDETA
÷2
RXCLKA+
RXCLKA–
LFIB
RXDB[0..9]
RXOPB
COMDETB
÷2
RXCLKB+
RXCLKB–
LFIC
RXDC[0..9]
RXOPC
COMDETC
÷2
RXCLKC+
RXCLKC–
LFID
RXDD[0..9]
RXOPD
COMDETD
÷2
RXCLKD+
RXCLKD–
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CYV15G0402DXB 전자부품, 판매, 대치품
CYP15G0402DXB
CYV15G0402DXB
Pin Descriptions CYP(V)15G0402DXB Quad HOTLink II™ SERDES
Name
I/O Characteristics Signal Description
Transmit Path Data Signals
TXPERA
TXPERB
TXPERC
TXPERD
LVTTL1 Output,
changes relative to
REFCLK[4]
Transmit Path Parity Error. Active HIGH. Asserted (HIGH) if parity checking is enabled
and a parity error is detected at the shifter. This output is HIGH for one transmit character
clock period to indicate detection of a parity error in the character presented to the
shifter.
If a parity error is detected, the character in error is replaced with the 10-bit character,
1001111000, to force a corresponding bad-character detection at the remote end of the
link. This replacement takes place only when parity checking is enabled (PARCTL
LOW).
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When BIST is enabled for the specific transmit channel, BIST progress is presented on
these outputs. Once every 511 character times, the associated TXPERx signal will pulse
HIGH for one transmit-character clock period to indicate a complete pass through the
BIST sequence.
These outputs also provide indication of a transmit Phase-Align Buffer underflow or
overflow. When the transmit Phase-Align Buffers are enabled (TXCKSEL LOW, or
TXCKSEL = LOW and TXRATE = HIGH), if an underflow or overflow condition is
detected, TXPERx for the channel in error is asserted and remains asserted until either
an atomic Word Sync Sequence is transmitted or TXRST is sampled LOW to re-center
the transmit Phase-Align Buffers.
TXDA[9:0]
TXDB[9:0]
TXDC[9:0]
TXDD[9:0]
LVTTL Input,
Transmit Data Inputs. These inputs are captured on the rising edge of the transmit
synchronous,
interface clock as selected by TXCKSEL and passed to the transmit shifter.
sampled by the
respective TXCLKx
TXDx[9:0] specify the specific transmission character to be sent.
or REFCLK[4]
TXOPA
TXOPB
TXOPC
TXOPD
LVTTL Input,
Transmit Path Odd Parity. When parity checking is enabled (PARCTL LOW), the
synchronous,
ODD parity captured at these inputs is XORed with the bits on the associated TXDx bus
sampled by the
to verify the integrity of the captured character.
respective TXCLKx
or REFCLK[4]
Transmit Path Clock and Control
TXCLKO±
TXCKSEL
LVTTL Output
Transmit Clock Output. This true and complement clock is synthesized by the transmit
PLL and is synchronous to the internal transmit character clock. It has the same
frequency as REFCLK (when TXRATE = LOW), or twice the frequency of REFCLK
(when TXRATE = HIGH). This output clock has no direct phase relationship to REFCLK.
Three-level Select[5] Transmit Clock Select.
Static Control Input Selects the clock source used to write data into the transmit Input Register of the
transmit channel(s)
When LOW, all four input registers are clocked by REFCLK.
When TXCKSEL is MID, TXCLKxis used as the input register clock for the associated
TXDx[9:0] and TXOPx.
When HIGH, TXCLKAis used to clock data into the Input Register for all channels.
When TXCKSEL = MID or HIGH (TXCLKx or TXCLKA selected to clock input register),
TXRATE = HIGH (Half-rate REFCLK) is an invalid mode of operation.
TXCLKA
TXCLKB
TXCLKC
TXCLKD
LVTTL Clock Input
asynchronous,
internal pull-up
Transmit Path Input Clocks. These inputs are only used when TXCKSEL LOW.
These clocks must be frequency-coherent to REFCLK, but may be offset in phase.
The internal operating phase of each input clock (relative to REFLCK or TXCLKO±) is
adjusted when TXRST = LOW and locked when TXRST = HIGH.
Notes:
4. When REFCLK is configured for half-rate operation (TXRATE = HIGH), these inputs are sampled (or the outputs change) relative to both the rising and falling
edges of REFCLK
5. Three-level select inputs are used for static configuration. They are ternary (not binary) inputs that make use of non-standard logic levels of LOW, MID, and
HIGH. The LOW level is usually implemented by direct connection to VSS (ground). The HIGH level is usually implemented by direct connection to VCC. When
not connected or allowed to float, a three-level select input will self-bias to the MID level.
Document #: 38-02057 Rev. *G
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CYV15G0402DXB

Quad HOTLink IIBT SERDES

Cypress Semiconductor
Cypress Semiconductor

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