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PDF CYV15G0403DXB Data sheet ( Hoja de datos )
| Número de pieza | CYV15G0403DXB | |
| Descripción | Independent Clock Quad HOTLink II-TM Transceiver | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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PRELIMINARY
CYP15G0403DXB
CYV15G0403DXB
Independent Clock Quad HOTLink II™ Transceiver
Features
• Quad channel transceiver for 195- to 1500-MBaud serial
signaling rate
www.DataSheet4U.com— Aggregate throughput of up to 12 Gbits/second
• Second-generation HOTLink® technology
• Compliant to multiple standards
— ESCON, DVB-ASI, SMPTE-292M, SMPTE-259M,
Fibre Channel and Gigabit Ethernet (IEEE802.3z)
— 8B/10B coded data or 10 bit uncoded data
• Truly independent channels
— Each channel can operate at a different signaling
rate
— Each channel can transport a different type of data
• Selectable input/output clocking options
• Internal phase-locked loops (PLLs) with no external
PLL components
• Dual differential PECL-compatible serial inputs per
channel
— Internal DC-restoration
• Dual differential PECL-compatible serial outputs per
channel
— Source matched for 50 transmission lines
— No external bias resistors required
— Signaling-rate controlled edge-rates
• MultiFrame™ Receive Framer provides alignment
options
— Bit and byte alignment
— Comma or Full K28.5 detect
— Single or Multi-byte Framer for byte alignment
— Low-latency option
• Synchronous LVTTL parallel interface
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Compatible with
— Fiber-optic modules
— Copper cables
— Circuit board traces
• Per-channel Link Quality Indicator
— Analog signal detect
— Digital signal detect
• Low-power 3W @ 3.3V typical
• Single 3.3V supply
• 256-ball thermally enhanced BGA
• 0.25 BiCMOS technology
Functional Description
The CYP(V)15G0403DXB[1] Independent Clock Quad
HOTLink II™ Transceiver is a point-to-point or point-to-multi-
point communications building block enabling transfer of data
over a variety of high-speed serial links like optical fiber,
balanced, and unbalanced copper transmission lines. The
signaling rate can be anywhere in the range of 195 to 1500
MBaud per serial link. Each channel operates independently
with its own reference clock allowing different rates. Each
transmit channel accepts parallel characters in an Input
Register, encodes each character for transport, and then
converts it to serial data. Each receive channel accepts serial
data and converts it to parallel data, decodes the data into
characters, and presents these characters to an Output
Register. Figure 1 illustrates typical connections between
independent host systems and corresponding
CYP(V)15G0403DXB chips.
10
10
Serial Links
10
10
10
10
10
10
Independent
CYP(V)15G0403DXB
Serial Links
Serial Links
Independent
CYP(V)15G0403DXB
10
10
10
10
10
10
Serial Links
Backplane or
Cabled
Connections
10
10
Figure 1. HOTLink II™ System Connections
Note:
1. CYV15G0403DXB refers to the SMPTE-compliant devices. CYP15G0403DXB refers to the non-SMPTE devices. CYP(V)15G0403DXB corresponds to both
SMPTE and non-SMPTE devices.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-02065 Rev. *C
Revised June 11, 2004
1 page  
PRELIMINARY
Device Configuration and Control Block Diagram
WREN
ADDR[3:0]
DATA[7:0]
www.DataSheet4U.com
Device Configuration
and Control Interface
RFMODE[A..D][1:0]
RFEN[A..D]
FRAMCHAR[A..D]
DECMODE[A..D]
RXBIST[A..D]
RXCKSEL[A..D]
DECBYP[A..D]
RXRATE[A..D]
SDASEL[2..1][A..D][1:0]
RXPLLPD[A..D]
TXRATE[A..D]
TXCKSEL[A..D]
PABRST[A..D]
TXBIST[A..D]
OE[2..1][A..D]
ENCBYP[A..D]
GLEN[11..0]
FGLEN[2..0]
CYP15G0403DXB
CYV15G0403DXB
= Internal Signal
Pin Configuration (Top View)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A
IN
C1–
OUT
C1–
IN
C2–
OUT
C2–
VCC
IN
D1–
OUT GND IN
D1– D2–
OUT
D2–
IN
A1–
OUT GND IN
A1– A2–
OUT
A2–
VCC
IN
B1–
OUT
B1–
IN
B2–
OUT
B2–
B
IN
C1+
OUT
C1+
IN
C2+
OUT
C2+
VCC
IN
D1+
OUT GND IN
D1+ D2+
OUT
D2+
IN
A1+
OUT GND IN
A1+ A2+
OUT
A2+
VCC
IN
B1+
OUT
B1+
IN
B2+
OUT
B2+
C
TDI
TMS INSELC INSELB VCC
ULCD ULCC GND
DATA
[7]
DATA
[5]
DATA
[3]
DATA
[1]
GND
NC
SPD
SELD
VCC
LDTD TRST LPEND TDO
EN
D
TCLK RESET INSELD INSELA VCC
ULCA SPD GND
SELC
DATA
[6]
DATA
[4]
DATA
[2]
DATA
[0]
GND LPENB ULCB
VCC
LPENA LTEN1 SCAN TMEN3
EN2
E VCC VCC VCC VCC
VCC VCC VCC VCC
F RX RX TX NC
DC[6] DC[7] DC[0]
G TX
TX TX
DC[7] WREN DC[4] DC[1]
H GND GND GND GND
NC
SPD
SELB
GND
RX TX RX
STB[1] CLKOB STB[0]
LP SPD RX
ENC SELA DB[1]
GND GND GND
J TX TX TX TX
CTC[1] DC[5] DC[2] DC[3]
K
RX REF TX
TX
DC[2] CLKC– CTC[0] CLKC
L
RX REF LFIC TX
DC[3] CLKC+
DC[6]
M RX RX NC TX
DC[4] DC[5]
ERRC
N GND GND GND GND
RX
STB[2]
RX
DB[3]
RX
DB[0]
RX
DB[4]
RX
DB[5]
RX
DB[7]
RX
DB[2]
LFIB
RX RX RX
DB[6] CLKB+ CLKB–
REF REF TX
CLKB+ CLKB– ERRB
GND GND GND
TX
DB[6]
TX
CLKB
GND
P RX RX RX RX
DC[1] DC[0] STC[0] STC[1]
R RX TX RX RX
STC[2] CLKOC CLKC+ CLKC–
T VCC VCC VCC VCC
TX
DB[5]
TX
DB[1]
VCC
TX
DB[4]
TX
DB[0]
VCC
TX
DB[3]
TX
CTB[1]
VCC
TX
DB[2]
TX
DB[7]
VCC
U
TX
DD[0]
TX
DD[1]
TX TX
DD[2] CTD[1]
VCC
RX
DD[2]
RX
DD[1]
GND TX ADDR REF TX
CTA[1] [0] CLKD– DA[1]
GND
TX TX
DA[4] CTA[0]
VCC
RX TX RX RX
DA[2] CTB[0] STA[2] STA[1]
V
TX TX TX RX
DD[3] DD[4] CTD[0] DD[6]
VCC
RX RX GND RX ADDR REF TX GND TX TX
DD[3] STD[0]
STD[2] [2] CLKD+ CLKOA
DA[3] DA[7]
VCC
RX RX RX RX
DA[7] DA[3] DA[0] STA[0]
W
TX
DD[5]
TX
DD[7]
LFID
RX
CLKD–
VCC
RX RX GND ADDR ADDR RX TX GND TX TX
DD[4] STD[1]
[3] [1] CLKA+ ERRA
DA[2] DA[6]
VCC
LFIA REF RX
RX
CLKA+ DA[4] DA[1]
Y
TX
DD[6]
TX
CLKD
RX RX
DD[7] CLKD+
VCC
RX RX GND TX
DD[5] DD[0]
CLKOD
NC
TX RX GND
CLKA CLKA–
TX
DA[0]
TX
DA[5]
VCC
TX REF RX
ERRD CLKA– DA[6]
RX
DA[5]
Document #: 38-02065 Rev. *C
Page 5 of 43
5 Page 
PRELIMINARY
CYP15G0403DXB
CYV15G0403DXB
Pin Definitions (continued)
CYP(V)15G0403DXB Quad HOTLink II Transceiver
Name
Analog I/O
OUTA1±
OUTB1±
OUTC1±
OUTD1±
www.DataSheet4U.cOomUTA2±
OUTB2±
OUTC2±
OUTD2±
INA1±
INB1±
INC1±
IND1±
INA2±
INB2±
INC2±
IND2±
JTAG Interface
TMS
TCLK
TDO
TDI
TRST
Power
VCC
GND
I/O Characteristics Signal Description
CML Differential
Output
CML Differential
Output
Differential Input
Differential Input
Primary Differential Serial Data Output. The OUTx1± PECL-compatible CML
outputs (+3.3V referenced) are capable of driving terminated transmission lines or
standard fiber-optic transmitter modules, and must be AC-coupled for PECL-
compatible connections.
Secondary Differential Serial Data Output. The OUTx2± PECL-compatible CML
outputs (+3.3V referenced) are capable of driving terminated transmission lines or
standard fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible
connections.
Primary Differential Serial Data Input. The INx1± input accepts the serial data
stream for deserialization and decoding. The INx1± serial stream is passed to the
receive CDR circuit to extract the data content when INSELx = HIGH.
Secondary Differential Serial Data Input. The INx2± input accepts the serial
data stream for deserialization and decoding. The INx2± serial stream is passed
to the receiver CDR circuit to extract the data content when INSELx = LOW.
LVTTL Input,
internal pull-up
LVTTL Input,
internal pull-down
3-State LVTTL
Output
LVTTL Input,
internal pull-up
LVTTL Input,
internal pull-up
Test Mode Select. Used to control access to the JTAG Test Modes. If maintained
high for 5 TCLK cycles, the JTAG test controller is reset.
JTAG Test Clock.
Test Data Out. JTAG data output buffer. High-Z while JTAG test mode is not
selected.
Test Data In. JTAG data input port.
JTAG reset signal. When asserted (LOW), this input asynchronously resets the
JTAG test access port controller.
+3.3V Power.
Signal and Power Ground for all internal circuits.
CYP(V)15G0403DXB HOTLink II Operation
The CYP(V)15G0403DXB is a highly configurable,
independent clocking, quad-channel transceiver
designed to support reliable transfer of large quantities
of data, using high-speed serial links from multiple
sources to multiple destinations. This device supports
four single-byte channels.
CYP(V)15G0403DXB Transmit Data Path
Input Register
The bits in the Input Register for each channel support
different assignments, based on if the input data is encoded or
unencoded. These assignments are shown in Table 1.
When the ENCODER is enabled, each input register captures
eight data bits and two control bits on each input clock cycle.
When the Encoder is bypassed, the control bits are part of the
pre-encoded 10-bit character.
When the Encoder is enabled, the TXCTx[1:0] bits are inter-
preted along with the associated TXDx[7:0] character to
generate a specific 10-bit transmission character.
Phase-Align Buffer
Data from each Input Register is passed to the associated
Phase-Align Buffer, when the TXDx[7:0] and TXCTx[1:0] input
registers are clocked using TXCLKx¦ (TXCKSELx = 0 and
TXRATEx = 0). When the TXDx[7:0] and TXCTx[1:0] input
registers are clocked using REFCLKx± (TXCKSELx = 1) and
REFCLKx± is a full-rate clock, the associated Phase
Alignment Buffer in the transmit path is bypassed. These
buffers are used to absorb clock phase differences between
the TXCLKx input clock and the internal character clock for
that channel.
Once initialized, TXCLKx is allowed to drift in phase as much
as ±180 degrees. If the input phase of TXCLKx drifts beyond
the handling capacity of the Phase Align Buffer, TXERRx is
Document #: 38-02065 Rev. *C
Page 11 of 43
11 Page | ||
| Páginas | Total 43 Páginas | |
| PDF Descargar | [ Datasheet CYV15G0403DXB.PDF ] | |
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