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6168LA70DB 데이터시트 PDF




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6168LA70DB 데이터시트, 핀배열, 회로
CMOS Static RAM
16K (4K x 4-Bit)
IDT6168SA
IDT6168LA
Features
x High-speed (equal access and cycle time)
– Military: 25/45ns (max.)
– Industrial: 25ns (max.)
– Commercial: 15/20/25ns (max.)
x Low power consumption
x Battery backup operation—2V data retention voltage
www.DataSheet4U(.IcDoTm6168LA only)
x Available in high-density 20-pin ceramic or plastic DIP and
20-pin leadless chip carrier (LCC)
x Produced with advanced CMOS high-performance
technology
x CMOS process virtually eliminates alpha particle
soft-error rates
x Bidirectional data input and output
x Military product compliant to MIL-STD-883, Class B
Description
The IDT6168 is a 16,384-bit high-speed static RAM organized
as 4K x 4. It is fabricated using lDT’s high-performance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective approach for
high-speed memory applications.
Access times as fast 15ns are available. The circuit also offers a
reduced power standby mode. When CS goes HIGH, the circuit will
automatically go to, and remain in, a standby mode as long as CS remains
HIGH. This capability provides significant system-level power and cooling
savings. The low-power (LA) version also offers a battery backup data
retention capability where the circuit typically consumes only 1µW
operating off a 2V battery. All inputs and outputs of the IDT6168 are
TTL-compatible and operate from a single 5V supply.
The IDT6168 is packaged in either a space saving 20-pin, 300-mil
ceramic or plastic DIP or a 20-pin LCC providing high board-level
packing densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
Functional Block Diagram
A0
ADDRESS
DECODER
16,384-BIT
MEMORY ARRAY
VCC
GND
A11
I/O0
I/O CONTROL
I/O1
INPUT
DATA
I/O2 CONTROL
I/O3
,
CS
WE
©2000 Integrated Device Technology, Inc.
1
3090 drw 01
FEBRUARY 2001
DSC-3090/05




6168LA70DB pdf, 반도체, 판매, 대치품
IDT6168SA/LA
CMOS Static RAM 16K (4K x 4-Bit)
Military, Industrial, and Co mmercial Temperature Ranges
Data Retention Characteristics (LA Version Only)
VLC = 0.2V, VHC = VCC – 0.2V
IDT6168LA
Symbol
Parameter
Test Condition
Min. Typ.(1) Max. Unit
VDR VCC for Data Retention
2.0 ____ V____
ICCDR Data Retention Current
CS > VHC
VIN > VHC
or < VLC
MIL.
COM'L.
____
____
____
____
0.5(2)
1.0(3)
0.5(2)
1.0(3)
100(2)
150(3)
20(2)
30(3)
µA
µA
tCDR(5)
www.DataSheett4RU(5).com
Chip Deselect to Data
Retention Time
Operation Recovery Time
0
tRC(4)
____
____
____ ns
____ ns
NOTES:
1. TA = +25°C.
2. at VCC = 2V
3. at VCC = 3V
4. tRC = Read Cycle Time.
5. This parameter is guaranteed by device characterization, but is not production tested.
3090 tbl 10
Low VCC Data Retention Waveform
DATA
RETENTION
MODE
VCC 4.5V
tCDR
VDR 2V
CS VIH VDR
4.5V
tR
VIH
,
3090 drw 03
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
5V
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
3090 tbl 11
DATA OUT
255
480
30pF*
DATAOUT
255
5V
480
5pF*
3090 drw 04
Figure 1. AC Test Load
*Includes scope and jig capacitances
4
Figure 2. AC Test Load
(for tCHZ, tCLZ, tWHZ and tOW)
3090 drw 05

4페이지










6168LA70DB 전자부품, 판매, 대치품
IDT6168SA/LA
CMOS Static RAM 16K (4K x 4-Bit)
Military, Industrial, and Co mmercial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,5)
t WC
ADDRESS
t AW
CS
t AS
tWP
t
(3)
WR
WE
www.DataSheet4DUA.TcoAmOUT
t WHZ (6)
PREVIOUS DATA VALID (4)
t DW
tOW (6)
t DH
(6)
t CHZ
DATA
VALID
(4)
,
DATAIN
DATA VALID
3090 drw 08
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,2,5)
t WC
ADDRESS
t AW
CS
tAS
WE
t CW
(3)
tWR
t DW
t DH
DATAIN
DATA VALID
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. During this period, the I/O pins are in the output state and input signals should not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high impedance state.
6. Transition is measured ±200mV from steady state.
,
3090 drw 09
6.472

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