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PDF BIT3193 Data sheet ( Hoja de datos )

Número de pieza BIT3193
Descripción High Performance PWM Controller Application Note
Fabricantes Beyond 
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No Preview Available ! BIT3193 Hoja de datos, Descripción, Manual

Beyond Innovation Technology Co., Ltd.
BIT3193
www.DataSheet4U.com
BIT3193
High Performance PWM Controller
Version 1.0
Notice
Information contained in this document is believed to be accurate and reliable and subject to change without
notice.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of Beyond Innovation Technology Co., Ltd.
The information presented in this document does not form part of any quotation or contract. BiTEK is not liable
for any consequence of the usage and/or application of the information contained therein. Publication thereof does
not convey nor imply any license under patent or other industrial or intellectual property rights.
BiTEK
This product is not designed for use in life support appliances, devices, or systems where malfunction of this
product can reasonably be expected to result in personal injury. BiTEK customers’ using or Mselaliyng3t1hi,s2p0ro0d5uct for
use in such applications shall do so at their own risk and agree to fully indemnify BiTEK for any damage resulting from
such improper use or sale.
DCC CONTROLLED
05/03/14
Preliminary
Confidential, for authorized user only
page i of 14

1 page




BIT3193 pdf
Beyond Innovation Technology Co., Ltd.
BIT3193
2.2. Clock and ramp wave generator
A capacitor is connected in CTOSC pin, which can produce a triangular wave; the frequency of this wave is
also called the oscillation frequency, shown as Fig. 3. Comparing with 0.5V and 2.25V, the two current sources
charged and discharged then generate the necessary triangular wave. The relationship of frequency and
capacitor value is shown as Fig. 4. In addition, BIT3193 is a two output signals with 180 degree out of phase
and its triangular frequency is double of its output frequency.
www.DataSheet4U.com
2.25V
0.5V
+
-
CTOSC
Fig. 3 The schematic of ramp wave generator
Fig. 4 The relationship of CTOSC and frequency
The generated frequency can be referred as following equation:
F =HFPWM
K HF ,
CCTOSC
KHF = 8.2e - 5
If the required frequency is 50kHz, the selected triangular wave frequency is 100kHz, therefore we can know:
100kHz = 8.2e 5
CCTOSC
And choose a 820pF capacitor and connect it to CTOSC pin.
In addition, considering about temperature factor and the tolerance of capacitor, to choose the NPO type with
5% tolerance so as to meet the requirement, 8% design specification, because of the 3% frequency tolerance
of BIT3193. For a 50 KHz frequency design, the maximum tolerance of 8% equals 4KHz.
2.3. LOAD Resistor vs. CTOSC Frequency
BIT3193 supports the higher start-up frequency when a resistor connected to its LOAD pin, shown as Fig 5.
The function of LOAD pin is related to ISEN pin. When the voltage of ISEN pin is lower than 1.3V, the internal
B i T E Kswitch (connected to LOAD pin) is “closed” that makes BIT3193 generate a higher start-up frequency. When the
voltage of ISEN pin is higher than 1.3V, the internal switch connected is “opened” that makes BIT3193 generate a
May 31, 2005
normal operation frequency. The relationship of LOAD resistor and CTOSC frequency deviation is shown as Fig.
6. DCC CONTROLLED
05/03/14
Preliminary
Confidential, for authorized user only
page 3 of 14

5 Page





BIT3193 arduino
Beyond Innovation Technology Co., Ltd.
BIT3193
www.DataSheet4U.com
CLAMP
TIME_INI
60uA
INN
CMP
Rs +
1.25V
-
2.25V
0.5V
Fig. 14 The scheme of over voltage clamping
Another function of CLAMP pin is shown as Fig. 15. When voltage level of ISEN pin is higher than 2.5V then
NOUT has PWM output and CLAMP level is higher than 2V (e. g. 2.5V). BIT3193 will shut down its output after
counting 14 cycles based on CTOSC frequency.
2.5V
1.5V
NOUT
CTOSC
14 CYCLES
Fig. 15 Delay of CLAMP protection
BiTEK
2.9. Output driving circuit
NOUT of BIT3193 is controlled by PWMOUT, protection circuit and ON/OFF assMocaiayte3d1b,y20an05AND gate,
shown as Fig. 16.
The
output
PWM
signal
level
is
IC_VDD
and
ground
by
its output
DCC
dCriviOngNMOTSRFEOT cLircLuEit.
D
05/03/14
Preliminary
Confidential, for authorized user only
page 9 of 14

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