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E5108AGBG PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 E5108AGBG
기능 EDE5108AGBG
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E5108AGBG 데이터시트, 핀배열, 회로
DATA SHEET
512M bits DDR2 SDRAM
EDE5108AGBG (64M words × 8 bits)
Specifications
Density: 512M bits
Organization
16M words × 8 bits × 4 banks
Package: 60-ball FBGA
www.DataSheet4U.comLead-free (RoHS compliant)
Power supply: VDD, VDDQ = 1.8V ± 0.1V
Data rate: 667Mbps/533Mbps (max.)
1KB page size
Row address: A0 to A13
Column address: A0 to A9
Four internal banks for concurrent operation
Interface: SSTL_18
Burst lengths (BL): 4, 8
Burst type (BT):
Sequential (4, 8)
Interleave (4, 8)
/CAS Latency (CL): 3, 4, 5
Precharge: auto precharge option for each burst
access
Driver strength: normal/weak
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8μs at 0°C TC ≤ +85°C
3.9μs at +85°C < TC ≤ +95°C
Operating case temperature range
TC = 0°C to +95°C
Features
Double-data-rate architecture; two data transfers per
clock cycle
The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
Programmable RDQS, /RDQS output for making × 8
organization compatible to × 4 organization
/DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation
Document No. E0917E30 (Ver. 3.0)
Date Published September 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2006




E5108AGBG pdf, 반도체, 판매, 대치품
EDE5108AGBG
CONTENTS
Specifications.................................................................................................................................................1
Features.........................................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Pin Configurations .........................................................................................................................................3
Electrical Specifications.................................................................................................................................5
Block Diagram .............................................................................................................................................23
Pin Function.................................................................................................................................................24
Command Operation ...................................................................................................................................26
Simplified State Diagram .............................................................................................................................33
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Operation of DDR2 SDRAM ........................................................................................................................34
Package Drawing ........................................................................................................................................71
Recommended Soldering Conditions..........................................................................................................72
Data Sheet E0917E30 (Ver. 3.0)
4

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E5108AGBG 전자부품, 판매, 대치품
EDE5108AGBG
DC Characteristics 1 (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V)
Parameter
Operating current
(ACT-PRE)
Symbol Grade
IDD0
-6E
-5C
max.
×8
115
110
Operating current
(ACT-READ-PRE)
IDD1
-6E
-5C
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Precharge power-down
standby current
IDD2P
-6E
-5C
130
125
10
10
Precharge quiet
standby current
IDD2Q
-6E
-5C
25
25
Idle standby current IDD2N
-6E
-5C
Active power-down
standby current
IDD3P-F
-6E
-5C
IDD3P-S
-6E
-5C
35
30
40
40
25
25
Active standby current IDD3N
-6E
-5C
70
65
Operating current
(Burst read operating)
IDD4R
-6E
-5C
230
190
Operating current
(Burst write operating)
IDD4W
-6E
-5C
220
190
Unit Test condition
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
mA CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
one bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
mA tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
mA CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA
CKE is H, /CS is H;
Other control and address bus inputs are
SWITCHING;
Data bus inputs are SWITCHING
all banks open;
mA tCK = tCK (IDD);
CKE is L;
Fast PDN Exit
MRS(12) = 0
Other control and address
mA
bus inputs are STABLE; Slow PDN Exit
Data bus inputs are
MRS(12) = 1
FLOATING
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
tRP = tRP (IDD);
mA CKE is H, /CS is H between valid commands;
Other control and address bus inputs are
SWITCHING;
Data bus inputs are SWITCHING
all banks open, continuous burst reads,
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD),
mA tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD),
mA tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Data Sheet E0917E30 (Ver. 3.0)
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E5108AGBG

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