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E5108ASE PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 E5108ASE
기능 EDE5108ASE
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E5108ASE 데이터시트, 핀배열, 회로
PRELIMINARY DATA SHEET
512M bits DDR2 SDRAM
EDE5104AGSE (128M words × 4 bits)
EDE5108AGSE (64M words × 8 bits)
Description
The EDE5104AGSE is a 512M bits DDR2 SDRAM
organized as 33,554,432 words × 4 bits × 4 banks.
The EDE5108AGSE is a 512M bits DDR2 SDRAM
www.DataSheet4Uo.crogmanized as 16,777,216 words × 8 bits × 4 banks.
They are packaged in 60-ball FBGA (µBGA) package.
Features
Power supply: VDD, VDDQ = 1.8V ± 0.1V
Double-data-rate architecture: two data transfers per
clock cycle
Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
Four internal banks for concurrent operation
Data mask (DM) for write data
Burst lengths: 4, 8
/CAS Latency (CL): 3, 4, 5
Auto precharge operation for each burst access
Auto refresh and self refresh modes
Average refresh period
7.8µs at 0°C TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
SSTL_18 compatible I/O
Posted CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
Programmable RDQS, /RDQS output for making × 8
organization compatible to × 4 organization
/DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation.
FBGA (µBGA) package with lead free solder
(Sn-Ag-Cu)
RoHS compliant
Document No. E0715E20 (Ver. 2.0)
Date Published July 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005




E5108ASE pdf, 반도체, 판매, 대치품
EDE5104AGSE, EDE5108AGSE
CONTENTS
Description.....................................................................................................................................................1
Features.........................................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Pin Configurations .........................................................................................................................................3
Electrical Specifications.................................................................................................................................5
Block Diagram .............................................................................................................................................15
Pin Function.................................................................................................................................................16
Command Operation ...................................................................................................................................18
Simplified State Diagram .............................................................................................................................25
www.DataSheet4U.com
Operation of DDR2 SDRAM ........................................................................................................................26
Package Drawing ........................................................................................................................................62
Recommended Soldering Conditions..........................................................................................................63
Preliminary Data Sheet E0715E20 (Ver. 2.0)
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E5108ASE 전자부품, 판매, 대치품
EDE5104AGSE, EDE5108AGSE
DC Characteristics 1 (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V)
Parameter
Operating current
(ACT-PRE)
Symbol Grade
IDD0
-6C
-6E
-5C
-4A
max.
×4
TBD
110
105
90
Operating current
(ACT-READ-PRE)
IDD1
www.DataSheet4U.com
Precharge power-
down standby current
IDD2P
-6C
-6E
-5C
-4A
-6C
-6E
-5C
-4A
Precharge quiet
standby current
IDD2Q
-6C
-6E
-5C
-4A
Idle standby current IDD2N
-6C
-6E
-5C
-4A
Active power-down
standby current
-6C
IDD3P-F
-6E
-5C
-4A
-6C
IDD3P-S
-6E
-5C
-4A
Active standby
current
IDD3N
-6C
-6E
-5C
-4A
TBD
125
120
105
TBD
10
10
8
TBD
25
25
20
TBD
35
30
25
TBD
40
40
35
TBD
25
25
20
TBD
70
65
60
Operating current
(Burst read operating)
IDD4R
-6C
-6E
-5C
-4A
TBD
200
170
140
Operating current
(Burst write
operating)
IDD4W
-6C
-6E
-5C
-4A
TBD
190
170
140
×8
TBD
115
110
95
TBD
130
125
110
TBD
10
10
8
TBD
25
25
20
TBD
35
30
25
TBD
40
40
35
TBD
25
25
20
TBD
70
65
60
TBD
230
190
150
TBD
220
190
150
Unit Test condition
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
mA CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
one bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
mA tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
mA CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open;
mA
tCK = tCK (IDD);
CKE is L;
Fast PDN Exit
MRS(12) = 0
Other control and
address bus inputs
mA
are STABLE;
Slow PDN Exit
Data bus inputs are MRS(12) = 1
FLOATING
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
mA
tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD),
mA tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD),
mA tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Preliminary Data Sheet E0715E20 (Ver. 2.0)
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E5108ASE

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