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PDF MT16VDDF12864H Data sheet ( Hoja de datos )

Número de pieza MT16VDDF12864H
Descripción SMALL-OUTLINE DDR SDRAM DIMM
Fabricantes Micron Technology 
Logotipo Micron Technology Logotipo



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SMALL-OUTLINE
DDR SDRAM DIMM
512MB, 1GB (x64)
200-PIN DDR SODIMM
MT16VDDF6464H – 512MB
MT16VDDF12864H – 1GB
For the latest data sheet, please refer to the MicronâWeb
site: www.micron.com/moduleds
Features
• 200-pin, small-outline, dual in-line memory
module (SODIMM)
• Fast data transfer rates: PC1600, PC2100, and PC2700
www.DataSheet4UUt.ciloimzes 200 MT/s, 266 MT/s, or 333 MT/s DDR
SDRAM components
• 512MB (64 Meg x 64), 1GB (128 Meg x 64)
• VDD = VDDQ = +2.5V
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data—i.e., source-synchronous data
capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 7.8125µs maximum average periodic refresh interval
• Serial Presence Detect (SPD) with EEPROM
• Programmable READ CAS latency
• Gold edge contacts
Table 1: Address Table
Refresh Count
Device Row Addressing
Device Bank Addressing
Device Configuration
Device Column Addressing
Module Rank Addressing
Figure 1: 200-Pin SODIMM (MO-224)
512MB Module
1GB Module
OPTIONS
• Package
200-pin SODIMM (standard)
200-pin SODIMM (lead-free)1
• Frequency/CAS Latency2
167 MHz (333 MT/s) CL = 2.5
133 MHz (266 MT/s) CL = 2
133 MHz (266 MT/s) CL = 2
133 MHz (266 MT/s) CL = 2.5
100 MHz (200 MT/s) CL = 2
MARKING
G
Y
-335
-262
-26A
-265
-202
NOTE: 1. Contact factory for availability of lead-free prod-
ucts.
2. CL = CAS (READ) latency.
512MB
8K
8K (A0–A12)
4 (BA0, BA1)
32 Meg x 8
1K (A0–A9)
2 (S0#, S1#)
1GB
8K
8K (A0–A12)
4 (BA0, BA1)
64 Meg x 8
2K (A0–A9, A11)
2 (S0#, S1#)
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
1
©2003 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

1 page




MT16VDDF12864H pdf
512MB, 1GB (x64)
200-PIN DDR SODIMM
Table 5: Pin Descriptions (Continued)
Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables on page 3 for more information
PIN NUMBERS
11, 25, 47, 61, 133, 147, 169,
183
SYMBOL
DQS0-DQS7
5, 6, 7, 8, 13, 14, 17, 18, 19,
20, 23, 24, 29, 30, 31, 32, 41,
42, 43, 44, 49, 50, 53, 54, 55,
56, 59, 60, 65, 66, 67, 68, 127,
www.DataShee1t42U8.,c1o2m9, 130, 135, 136, 139,
140, 141, 142, 145, 146, 151,
152, 153, 154, 163, 164, 165,
166, 171, 172, 175, 176, 177,
178, 181, 182, 187, 188, 189,
190
9, 10, 21, 22, 33, 34, 36, 45,
46, 57, 58, 69, 70, 81, 82, 92,
93, 94, 113, 114, 131, 132,
143, 144, 155, 156, 157, 167,
168, 179, 180, 191, 192
3, 4, 15, 16, 27, 28, 38, 39, 40,
51, 52, 63, 64, 75, 76, 87, 88,
90, 103, 104, 125, 126, 137,
138, 149, 150, 159, 161, 162,
173, 174, 185, 186, 200
197
85, 97, 98, 123, 124, 199
71, 72, 73, 74, 77, 78, 79, 80,
83, 84, 86, 89, 91
DQ0-DQ63
VDD
VSS
VDDSPD
NC
DNU
TYPE
Input/
Output
Input/
Output
DESCRIPTION
Data Strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
Data I/Os: Data bus.
Supply Power Supply: +2.5V ±0.2V.
Supply Ground.
Supply
Serial EEPROM positive power supply: +2.3V to +3.6V
No Connect: These pins should be left unconnected.
Do Not Use: These pins are not connected on this module, but
are assigned pins on other modules in this product family.
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.

5 Page





MT16VDDF12864H arduino
BA1 = 0) and will retain the stored information until it
is programmed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/ BA1 both LOW) to reset the DLL.
The extended mode register must be loaded when
all device banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating any subsequent operation. Violating either of
these requirements could result in unspecified opera-
tion.
www.DataSheet4U.com
DLL Enable/Disable
The DLL must be enabled for normal operation.
DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is enabled,
200 clock cycles must occur before a READ command
can be issued.
512MB, 1GB (x64)
200-PIN DDR SODIMM
Figure 7: Extended Mode Register
Definition Diagram
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Extended Mode
01 11
Operating Mode
DS DLL Register (Ex)
E0 DLL
0 Enable
1 Disable
E1 Drive Strength
0 Normal
1 Reduced
E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E22
0 0 0 0 0 0 0 00 0 0 0
– – – – – – – –– – – –
E1, E0
Valid
Operating Mode
Reserved
Reserved
NOTE:
1. BA1 and BA0 (E14 and E13) must be “0, 1” to select the
Extended Mode Register (vs. the base Mode Register).
2. The QFC# option is not supported.
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.

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