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PDF APL5330 Data sheet ( Hoja de datos )
| Número de pieza | APL5330 | |
| Descripción | Dual Input 2A Low Dropout Regulator | |
| Fabricantes | Anpec Electronics | |
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APL5330
Dual Input 2A Low Dropout Regulator
Features
General Description
• Fast Transient Response
• High Output Accuracy
- ±20mV over Load, Output Voltage Offset and
www.DataSheet4U.com Temperature
• Adjustable Output Voltage by External
Resistors
• Current-Limit Protection
• On-Chip Thermal Shutdown
• Shutdown for Standby or Suspend Mode
• Simple SOP-8 and SOP-8 with Thermal Pad
Packages
• Lead Free Available (RoHS Compliant)
Applications
The APL5330 integrates a power transistor to provide
regulated voltage with maximum output current of 2A.
It also incorporates current-limit, thermal shutdown and
shutdown control functions into a single chip.
The current-limit circuit limits the maximum output
current in overload or short-circuit conditions.
The on-chip thermal shutdown provides protection
against any combination of overload that would create
excessive junction temperature. The output voltage of
the APL5330 tracks the reference voltage on VREF
pin. A resistor divider connected to VREF pin is
usually used to provide reference voltage to the IC. In
addition, an external ceramic capacitor and an open-drain
transistor connected to VREF pin provides soft-start and
shutdown control. Applying and holding a voltage below
0.35V (typ.) to VREF shuts off the output.
• VGA Card Power
• Chip Set Power
Pin Configuration
VIN
GND
VREF
VOUT
1
2
3
4
8 VCNTL
7 VCNTL
6 VCNTL
5 VCNTL
SOP-8 (Top View)
VIN
GND
VREF
VOUT
1
2
3
4
8 NC
7 NC
6 VCNTL
5 NC
SOP-8-P (Top View)
NC = No internal connection
= Thermal Pad
(connected to GND plane for better heat dissipation)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright © ANPEC Electronics Corp.
Rev. A.1 - Jun., 2006
1
www.anpec.com.tw
1 page  
APL5330
Typical Characteristics
Current-Limit
vs. Junction Temperature
3.5
VIN = 2V
3 VOUT=1.2V
www.DataSheet4U.com
2.5
2
VCNTL = 5V
VCNTL = 3.3V
1.5
1
0.5
0
-50 -25 0 25 50 75 100 125
Junction Temperature (°C)
Quiescent VCNTL Current
vs. Junction Temperature
2500
IOUT= 0A
2000
1500
VCNTL = 5V
VCNTL = 3.3V
1000
500
0
-50 -25 0 25 50 75 100 125
Junction Temperature (°C)
VREF Threshold Voltage
vs. Junction Temperature
0.6
VCNTL = 5V
0.5
0.4
0.3 VCNTL = 3.3V
0.2
0.1
0
-50 -25 0 25 50 75 100 125
Junction Temperature (°C)
500
450
400
350
300
250
200
150
100
50
0
0
VREF Bias Current
vs. VREF Supply Voltage
VCNTL= 3.3V
VCNTL= 5V
0.5 1 1.5 2 2.5
VREF Supply Voltage (V)
3
Copyright © ANPEC Electronics Corp.
Rev. A.1 - Jun., 2006
5
www.anpec.com.tw
5 Page 
APL5330
Application Information (Cont.)
Output Capacitor
The APL5330 requires a proper output capacitor to
maintain stability and improve transient response.
The APL5330 can work stably with wide range of
capacitance and ESR (equivalent series resistance).
www.DataSheet4U.cAomlow-ESR solid tantalum, aluminum electrolytic or
ceramic output capacitor works extremely well and
provides good transient response and stability over
temperature.
The output capacitors also reduce the slew rate of load
current and help the APL5330 to minimize variations
of the output voltage. For this purpose, the low-ESR
capacitors which depend on the step size and slew
rate of load current are recommended.
25
20
15 Stable Region
10
5
0
10
Input Capacitor
100
Capacitance (uF)
1000
The input capacitors of VCNTL and VIN pins are not
required for stability but for supplying surge current
during large load transients. This will prevent the input
rail from dropping and improve the performance of the
APL5330. The parasitic inductors between voltage
sources or bulk capacitors and the power input pins
will limit the slew rate of the surge currents during
large load transients, resulting in voltage drop at VIN
and VCNTL pins.
For VCNTL pin, a capacitor of 1µF (ceramic chip
capacitor) or greater (aluminum electrolytic capacitor)
is recommended. For VIN pin, an aluminum electrolytic
capacitor (>47µF) is recommended. It is not necessary
to use low-ESR capacitors.
Layout and Thermal Consideration
The input capacitors for VINand VCNTL pins are normally
placed near each pin for good performances. Ceramic
decoupling capacitors of output must be placed as
close to the load to reduce the parasitic inductance of
traces. It is also recommended to place the APL5330
and output capacitors near the load for good load
regulation and load transient response. Please connect
the negative pins of the input and output capacitors
and the GND pin of the APL5330 to the power ground
plane of the load.
See figure 1. The SOP-8-P utilizes a bottom thermal
pad to minimize the thermal resistance of the package
and make the package suitable for high current
applications. The thermal pad is soldered to the top
ground pad connected to the internal or bottom ground
plane by several vias. The printed circuit board (PCB)
forms a heat sink and dissipates most of the heat
into ambient air. It is recommended that the vias have
proper size to retain solder and help heat conduction.
Thermal resistance consists of two main elements,
θJC (junction-to-case thermal resistance) and θCA
(case-to-ambient thermal resistance). θJC is specified
from the IC junction to the bottom of the thermal pad
directly below the die. θCA is the resistance from the
bottom of thermal pad to the ambient air and it includes
θCS (case-to-sink thermal resistance) and θSA (sink-to-
ambient thermal resistance). The specified path for
heat flow is the lowest resistance path and it dissipates
majority of the heat to the ambient air. Typically, θCA is
the dominant thermal resistance. Therefore, enlarging
Copyright © ANPEC Electronics Corp.
Rev. A.1 - Jun., 2006
11
www.anpec.com.tw
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet APL5330.PDF ] | |
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