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AD9858 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD9858은 전자 산업 및 응용 분야에서
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부품번호 AD9858 기능
기능 1 GSPS Direct Digital Synthesizer
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AD9858 데이터시트, 핀배열, 회로
1 GSPS Direct Digital Synthesizer
AD9858
FEATURES
1 GSPS internal clock speed
Up to 2 GHz input clock (selectable divide-by-2)
Integrated 10-bit DAC
Excellent phase noise and SFDR
32-bit programmable frequency register
Simplified 8-bit parallel and SPI serial control interface
Automatic frequency sweeping capability
4 frequency profiles
3.3 V power supply
Power dissipation: 2 W typical
Integrated programmable charge pump and phase
frequency detector with fast lock circuit
Isolated charge pump supply up to 5 V
Integrated 2 GHz mixer
APPLICATIONS
VHF/UHF LO synthesis
Tuners
Instrumentation
Agile clock synthesis
Cellular base station hopping synthesizers
Radars
SONET/SDH clock synthesis
GENERAL DESCRIPTION
The AD9858 is a direct digital synthesizer (DDS) featuring a
10-bit digital-to-analog converter (DAC) operating up to 1 GSPS.
The AD9858 uses advanced DDS technology coupled with an
internal high speed, high performance DAC to form a digitally
programmable, complete high frequency synthesizer capable of
generating a frequency-agile analog output sine wave at up to
400 MHz. The AD9858 is designed to provide fast frequency
hopping and fine tuning resolution (32-bit frequency tuning
word). The frequency tuning and control words are loaded into
the AD9858 via parallel (8-bit) or serial loading formats. The
AD9858 contains an integrated charge pump (CP) and phase
frequency detector (PFD) for synthesis applications requiring
the combination of a high speed DDS along with phase-locked
loop (PLL) functions. An analog mixer is also provided on chip
for applications requiring the combination of a DDS, PLL, and
mixer, such as frequency translation loops and tuners. The AD9858
also features a divide-by-2 on the clock input, allowing the external
reference clock to be as high as 2 GHz.
The AD9858 is specified to operate over the extended industrial
temperature range of –40°C to +85°C.
DIV
DIV
PD
CP
CPISET
FUNCTIONAL BLOCK DIAGRAM
LO LO
IF IF
RF RF
÷M
÷N
CHARGE
PUMP
PHASE
DETECTOR
DIGITAL PLL
ANALOG
MULTIPLIER
FREQUENCY ACCUMULATOR
PHASE ACCUMULATOR
AD9858
32
15
15
PHASE-TO-
AMPLITUDE
10
DAC
CONVERSION
DACISET
IOUT
IOUT
14
RESET
32
32
TIMING AND CONTROL LOGIC
CONTROL REGISTERS
POWER-
DOWN
LOGIC
÷8
PS0 PS1 I/O PORT
(SER/PAR)
Figure 1.
SYSCLK
M
U
X
÷2
FUD
SYNCLK
REFCLK
REFCLK
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2009 Analog Devices, Inc. All rights reserved.




AD9858 pdf, 반도체, 판매, 대치품
AD9858
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
General Description ......................................................................... 1 
Functional Block Diagram .............................................................. 1 
Revision History ............................................................................... 2 
Electrical Specifications ................................................................... 3 
Absolute Maximum Ratings............................................................ 6 
Thermal Performance.................................................................. 6 
Explanation of Test Levels ........................................................... 6 
ESD Caution.................................................................................. 6 
Pin Configuration and Function Descriptions............................. 7 
Typical Performance Characteristics ............................................. 9 
Theory of Operation ...................................................................... 14 
REVISION HISTORY
2/09—Rev. B to Rev. C
Changes to Features Section, General Description Section, and
Figure 1 .............................................................................................. 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 6
Added Thermal Performance Section ........................................... 6
Changes to Figure 3, Figure 4, and Figure 5.................................. 9
Changes to Figure 9, Figure 10 Caption, Figure 11 Caption,
Figure 13, and Figure 14 ................................................................ 10
Changes to Figure 17...................................................................... 11
Changes to Theory of Operation Section and DAC Output
Section.............................................................................................. 14
Changes to Charge Pump Section................................................ 15
Changes to Modes of Operation Section..................................... 16
Changes to Single-Tone Mode Section and Frequency Sweeping
Mode Section................................................................................... 17
Changes to SYNCLK and FUD Pins Section and Figure 33..... 18
Changes to I/O Port Functionality Section, Parallel
Programming Mode Section, and Figure 35............................... 20
Changes to Figure 36 and Serial Programming
Mode Section................................................................................... 21
Changes to Table 6.......................................................................... 22
Changes to Control Function Register (CFR) Section .............. 23
Changes to CFR[21]: Load Delta Frequency Timer Section .... 24
Changed CFR[14]: Sine/Cosine Select Bit Section to CFR[14]:
Enable Sine Output Bit Section..................................................... 24
Component Blocks..................................................................... 14 
Modes of Operation ................................................................... 16 
Synchronization.......................................................................... 18 
Programming the AD9858........................................................ 19 
Register Map ................................................................................... 22 
Register Bit Descriptions........................................................... 23 
Other Registers ........................................................................... 25 
User Profile Registers................................................................. 25 
Applications Information .............................................................. 27 
Evaluation Boards ...................................................................... 28 
Outline Dimensions ....................................................................... 29 
Warning ....................................................................................... 29 
Ordering Guide .......................................................................... 29 
Changes to Delta Frequency Tuning Word (DFTW) Section,
Delta Frequency Ramp Rate Word (DFRRW) Section, and
Phase Offset Control Section........................................................ 25
Changes to Profile Selection Section ........................................... 26
Deleted Frequency Tuning Control Section ............................... 27
Changed AD9858 Application Suggestions Section to
Applications Information Section ................................................ 27
Changes to Table 13 ....................................................................... 28
Added Exposed Paddle Notation to Outline Dimensions ........ 29
4/07—Rev. A to Rev. B
Changed EPAD to TQFP_EP............................................Universal
Updated Outline Dimensions....................................................... 31
11/03—Rev. 0 to Rev. A
Changes to Specifications.................................................................5
Moved ESD Caution to .....................................................................6
Moved Pin Configuration to............................................................7
Moved Pin Function Description to ...............................................8
Changes to Equations .................................................................... 19
Changes to Delta Frequency Ramp Rate Word (DFRRW)....... 27
4/03—Revision 0: Initial Version
Rev. C | Page 2 of 32

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AD9858 전자부품, 판매, 대치품
Parameter
TIMING CHARACTERISTICS
Serial Control Bus
Maximum Frequency
Minimum Clock Pulse Width Low (tPWL)
Minimum Clock Pulse Width High (tPWH)
Maximum Clock Rise/Fall Time
Minimum Data Setup Time (tDS)
Minimum Data Hold Time (tDH)
Maximum Data Valid Time (tDV)
Parallel Control Bus10
WR Minimum Low Time (tWRLOW)
WR Minimum High Time (tWRHIGH)
WR Minimum Period (tWR)
Address to WR Setup (tASU)
Address to WR Hold (tAHU)
Data to WR Setup (tDSU)
Data to WR Hold (tDHU)
Miscellaneous Timing Specifications
REFCLK to SYNCLK
FUD/PS[1:0] to SYNCLK Setup Time11
FUD/PS[1:0] to SYNCLK Hold Time11
REFCLK to SYNCLK Delay
DATA LATENCY (PIPELINE DELAY)
FTW/POW to DAC Output
DFTW to DAC Output
Temp Test Level Min
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full V
Full IV
Full IV
Full IV
25°C IV
25°C IV
5.5
15
7
0
3
6
9
3
0
3.5
0
4
0
83
99
1 REFCLK input is internally dc biased. AC coupling should be used.
2 Reference clock frequency is selected to ensure that the second harmonic is out of the bandwidth of interest.
3 PD inputs set at 400 MHz with divide-by-4 enabled.
4 The charge pump current is programmable in eight discrete steps; minimum value assumes current sharing.
5 For 0.75 V < VCP < CPVDD − 0.75 V.
6 These differential inputs are internally dc biased. AC coupling should be used.
7 The charge pump supply voltage can range from 4.75 V to 5.25 V.
8 DAC output is differential open collector.
9 For 1 dB output compression; input power measured at 50 Ω.
10 See Figure 35 and Figure 36 for timing diagrams.
11 See Figure 34 for timing diagram.
12 SYSCLK = REFCLK/x, where x is 1 or 2, as set using CFR[6].
AD9858
Typ Max
Unit
10
1
20
2.5
2.5 3
83
99
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYSCLK
cycles 12
SYSCLK
cycles12
Rev. C | Page 5 of 32

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