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PDF PJSMF05LC Data sheet ( Hoja de datos )

Número de pieza PJSMF05LC
Descripción 5-TVS/ZENER ARRAY
Fabricantes Pan Jit International 
Logotipo Pan Jit International Logotipo



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No Preview Available ! PJSMF05LC Hoja de datos, Descripción, Manual

PJSMF03LC Series
5-TVS/ZENER ARRAY FOR ESD AND LATCH-UP PROTECTION
This 5-TVS/Zener Array has been designed to Protect Sensitive Equipment against
ESD and to prevent Latch-Up events in CMOS circuitry, operating at 3.3V and 5V, as
well available for 12V, 15V, and 24V Systems. This TVS array offers an integrated
solution to protect up to 5 data lines where the board space is a premium.
SPECIFICATION FEATURES
100W Power Dissipation (8/20µs Waveform)
Low Leakage Current
Very Low Clamping Voltage
IEC61000-4-2 ESD 20kV air, 15kV Contact Compliance
www.DataSheet4U.cOomperating voltage options for 3.3V, 5V, 12V, 15V, and 24V
Industry Standard SOT363 (SC70-6L) Package
1
654
APPLICATIONS
Personal Digital Assistant (PDA)
SIM Card Port Protection (Mobile Phone)
Portable Instrumentation
Mobile Phones and Accessories
Memory Card Port Protection
123
SOT363
MAXIMUM RATINGS (Per Device)
Rating
Peak Pulse Power (8/20µs Waveform)
ESD Voltage (HBM)
Operating Temperature Range
Storage Temperature Range
Symbol
P pp
V ESD
TJ
Tstg
Value
100
25
-55 to +150
-55 to + 150
Units
W
kV
°C
°C
ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25°C
PJSMF03LC
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (820µs)
Clamping Voltage (8/20µs)
Off State Junction Capacitance
Off State Junction Capacitance
Symbol
VWRM
VBR
IR
Vc
Vc
Cj
Cj
Conditions
Min Typical Max
3.3
I BR = 10 mA
VR = 3.3V
I pp = 5A
I pp = 9A
0 Vdc Bias f = 1MHz
Between I/O pins and pin 2
3.3 Vdc Bias f = 1MHz
Between I/O pins and pin 2
4.7
5.6
250
7.5
9
160
90
Units
V
V
µA
V
V
pF
pF
9/14/2005
Page 1
www.panjit.com

1 page




PJSMF05LC pdf
PJSMF03LC Series
LAYOUT DIMENSIONS AND SUGGESTED PAD LAYOUT
www.DataSheet4U.com
9/14/2005
Page 5
www.panjit.com

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