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부품번호 | P4C1023 기능 |
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기능 | LOW POWER 128K x 8 SINGLE CHIP ENABLE CMOS STATIC RAM | ||
제조업체 | Pyramid Semiconductor | ||
로고 | |||
P4C1023/P4C1023L
LOW POWER 128K x 8
SINGLE CHIP ENABLE
CMOS STATIC RAM
FEATURES
VCC Current
— Operating: 35mA
— CMOS Standby: 100µA
Access Times
—55/70 ns
Single 5 Volts ±10% Power Supply
www.DataSheet4UE.caomsy Memory Expansion Using CE and OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—32-Pin 400 or 600 mil Ceramic DIP
—32-Pin Ceramic SOJ
DESCRIPTION
The P4C1023L is a 1 Megabit low power CMOS static
RAM organized as 128K x 8. The CMOS memory re-
quires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 55 ns and 70 ns are availale. CMOS is
utilized to reduce power consumption to a low level.
The P4C1023L device provides asynchronous opera-
tion with matching access and cycle times. Memory
locations are specified on address pins A0 to A16. Read-
ing is accomplished by device selection (CE low) and
output enabling (OE) while write enable (WE) remains
HIGH. By presenting the address under these condi-
tions, the data in the addressed memory location is pre-
sented on the data input/output pins. The input/output
pins stay in the HIGH Z state when either CE is HIGH or
WE is LOW.
The P4C1023L is packaged in a 32-pin 400 or 600 mil
ceramic DIP and in a 32-pin ceramic SOJ.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DIP (C10, C11), CERAMIC SOJ (CJ1)
TOP VIEW
Document # SRAM126 REV OR
Revised October 2005
1
P4C1023/P4C1023L
READ CYCLE NO. 1 (OE CONTROLLED)(1)
www.DataSheet4U.com
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
READ CYCLE NO. 3 (CE CONTROLLED)
Notes:
1. WE is HIGH for READ cycle.
2. CE and OE are LOW for READ cycle.
3. ADDRESS must be valid prior to, or coincident with later of
CE transition LOW.
4. Transition is measured ± 200 mV from steady state voltage prior
to change, with loading as specified in Figure 1. This parameter
is sampled and not 100% tested.
5. READ Cycle Time is measured from the last valid address to the
first transitioning address.
Document # SRAM126 REV OR
Page 4 of 11
4페이지 DATA RETENTION
Symbol
Parameter
Test Conditions
VDR VCC for Data Retention
ICCDR
tCDR
Data Retention Current
Chip Deselect to Data
Retention Time
CE ≥ VCC -0.2V,
VIN ≥ VCC -0.2V or VIN ≤ 0.2V
VDR = 2.0V
VDR = 3.0V
See Retention Waveform
tR Operating Recovery Time
www.DataShee1t4. UC.Eco1 m≥ VDR -0.2V, CE2 ≥ VDR -0.2V or CE2 ≤ 0.2V; or CE1 ≤ 0.2V, CE2 - 0.2V; VIN ≥ VDR -0.2V or VIN ≤ 0.2V
P4C1023/P4C1023L
Min Max Unit
2.0 5.5 V
50 µA
100 µA
0 ns
tRC ns
LOW VCC DATA RETENTION WAVEFORM
Document # SRAM126 REV OR
Page 7 of 11
7페이지 | |||
구 성 | 총 11 페이지수 | ||
다운로드 | [ P4C1023.PDF 데이터시트 ] |
당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는 |
구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
P4C1023 | LOW POWER 128K x 8 SINGLE CHIP ENABLE CMOS STATIC RAM | Pyramid Semiconductor |
P4C1023L | LOW POWER 128K x 8 SINGLE CHIP ENABLE CMOS STATIC RAM | Pyramid Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |