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P4C1023 데이터시트 PDF




Pyramid Semiconductor에서 제조한 전자 부품 P4C1023은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 P4C1023 자료 제공

부품번호 P4C1023 기능
기능 LOW POWER 128K x 8 SINGLE CHIP ENABLE CMOS STATIC RAM
제조업체 Pyramid Semiconductor
로고 Pyramid Semiconductor 로고


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P4C1023 데이터시트, 핀배열, 회로
P4C1023/P4C1023L
LOW POWER 128K x 8
SINGLE CHIP ENABLE
CMOS STATIC RAM
FEATURES
VCC Current
— Operating: 35mA
— CMOS Standby: 100µA
Access Times
—55/70 ns
Single 5 Volts ±10% Power Supply
www.DataSheet4UE.caomsy Memory Expansion Using CE and OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—32-Pin 400 or 600 mil Ceramic DIP
—32-Pin Ceramic SOJ
DESCRIPTION
The P4C1023L is a 1 Megabit low power CMOS static
RAM organized as 128K x 8. The CMOS memory re-
quires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 55 ns and 70 ns are availale. CMOS is
utilized to reduce power consumption to a low level.
The P4C1023L device provides asynchronous opera-
tion with matching access and cycle times. Memory
locations are specified on address pins A0 to A16. Read-
ing is accomplished by device selection (CE low) and
output enabling (OE) while write enable (WE) remains
HIGH. By presenting the address under these condi-
tions, the data in the addressed memory location is pre-
sented on the data input/output pins. The input/output
pins stay in the HIGH Z state when either CE is HIGH or
WE is LOW.
The P4C1023L is packaged in a 32-pin 400 or 600 mil
ceramic DIP and in a 32-pin ceramic SOJ.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DIP (C10, C11), CERAMIC SOJ (CJ1)
TOP VIEW
Document # SRAM126 REV OR
Revised October 2005
1




P4C1023 pdf, 반도체, 판매, 대치품
P4C1023/P4C1023L
READ CYCLE NO. 1 (OE CONTROLLED)(1)
www.DataSheet4U.com
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
READ CYCLE NO. 3 (CE CONTROLLED)
Notes:
1. WE is HIGH for READ cycle.
2. CE and OE are LOW for READ cycle.
3. ADDRESS must be valid prior to, or coincident with later of
CE transition LOW.
4. Transition is measured ± 200 mV from steady state voltage prior
to change, with loading as specified in Figure 1. This parameter
is sampled and not 100% tested.
5. READ Cycle Time is measured from the last valid address to the
first transitioning address.
Document # SRAM126 REV OR
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P4C1023 전자부품, 판매, 대치품
DATA RETENTION
Symbol
Parameter
Test Conditions
VDR VCC for Data Retention
ICCDR
tCDR
Data Retention Current
Chip Deselect to Data
Retention Time
CE VCC -0.2V,
VIN VCC -0.2V or VIN 0.2V
VDR = 2.0V
VDR = 3.0V
See Retention Waveform
tR Operating Recovery Time
www.DataShee1t4. UC.Eco1 mVDR -0.2V, CE2 VDR -0.2V or CE2 0.2V; or CE1 0.2V, CE2 - 0.2V; VIN VDR -0.2V or VIN 0.2V
P4C1023/P4C1023L
Min Max Unit
2.0 5.5 V
50 µA
100 µA
0 ns
tRC ns
LOW VCC DATA RETENTION WAVEFORM
Document # SRAM126 REV OR
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관련 데이터시트

부품번호상세설명 및 기능제조사
P4C1023

LOW POWER 128K x 8 SINGLE CHIP ENABLE CMOS STATIC RAM

Pyramid Semiconductor
Pyramid Semiconductor
P4C1023L

LOW POWER 128K x 8 SINGLE CHIP ENABLE CMOS STATIC RAM

Pyramid Semiconductor
Pyramid Semiconductor

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