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P4C1024L 데이터시트 PDF




Pyramid Semiconductor에서 제조한 전자 부품 P4C1024L은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 P4C1024L 자료 제공

부품번호 P4C1024L 기능
기능 LOW POWER 128K x 8 CMOS STATIC RAM
제조업체 Pyramid Semiconductor
로고 Pyramid Semiconductor 로고


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P4C1024L 데이터시트, 핀배열, 회로
P4C1024L
LOW POWER 128K x 8
CMOS STATIC RAM
FEATURES
VCC Current (Commercial/Industrial)
— Operating: 70mA/85mA
— CMOS Standby: 100µA/100µA
Access Times
—55/70 (Commercial or Industrial)
Single 5 Volts ±10% Power Supply
www.DataSheet4UE.caomsy Memory Expansion Using CE1, CE2 and OE
Inputs
DESCRIPTION
The P4C1024L is a 1,048,576-bit low power CMOS static
RAM organized as 128Kx8. The CMOS memory re-
quires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 55 ns and 70 ns are availale. CMOS is
utilized to reduce power consumption to a low level.
The P4C1024L device provides asynchronous opera-
tion with matching access and cycle times. Memory
FUNCTIONAL BLOCK DIAGRAM
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—32-Pin 600 mil Plastic and Ceramic DIP
—32-Pin 445 mil SOP
—32-Pin TSOP
locations are specified on address pins A0 to A16. Read-
ing is accomplished by device selection (CE1 low and
CE2 high) and output enabling (OE) while write enable
(WE) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory lo-
cation is presented on the data input/output pins. The
input/output pins stay in the HIGH Z state when either
CE1 or OE is HIGH or WE or CE2 is LOW.
The P4C1024L is packaged in a 32-pin TSOP, 445 mil
SOP, and a 600 mil PDIP.
PIN CONFIGURATION
DIP (P600, C10), SOP (S12)
TOP VIEW
See end of datasheet for TSOP pin configuration.
Document # SRAM125 REV C
Revised September 2006
1




P4C1024L pdf, 반도체, 판매, 대치품
P4C1024L
READ CYCLE NO. 1 (OE CONTROLLED)(1)
www.DataSheet4U.com
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
READ CYCLE NO. 3 (CE CONTROLLED)
Notes:
1. WE is HIGH for READ cycle.
2. CE1 and OE is LOW, and CE2 is HIGH for READ cycle.
3. ADDRESS must be valid prior to, or coincident with later of
CE1 transition LOW or CE2 transition HIGH.
4. Transition is measured ± 200 mV from steady state voltage prior
to change, with loading as specified in Figure 1. This parameter
is sampled and not 100% tested.
5. READ Cycle Time is measured from the last valid address to the
first transitioning address.
Document # SRAM125 REV C
Page 4 of 10

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P4C1024L 전자부품, 판매, 대치품
P4C1024L
DATA RETENTION
Symbol
Parameter
Test Conditions
Min
VDR
I (1)
CCDR
tCDR
tR
VCC for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operating Recovery Time
CE1 VCC -0.2V, CE2 0.2V,
VIN VCC -0.2V or VIN 0.2V
VDR = 2.0V
VDR = 3.0V
See Retention Waveform
2.0
0
5
www.DataSheet4U.c1o.mCE1 VDR -0.2V, CE2 VDR -0.2V or CE2 0.2V; or CE1 0.2V, CE2 - 0.2V; VIN VDR -0.2V or VIN 0.2V
Max Unit
5.5 V
30 µA
50 µA
ns
ms
LOW VCC DATA RETENTION WAVEFORM 1 (CE1 CONTROLLED)
LOW VCC DATA RETENTION WAVEFORM 2 (CE2 CONTROLLED)
DATA RETENTION MODE
VCC 4.5V
tCDR
VDR
CE2 VIL 2.2V
CE2 -0.2V
4.5V
tR
VIL
Document # SRAM125 REV C
Page 7 of 10

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