P4C1026 Datasheet PDF - Pyramid Semiconductor
| Part Number | P4C1026 | |
| Description | ULTRA HIGH SPEED 256K x 4 STATIC CMOS RAM | |
| Manufacturers | Pyramid Semiconductor | |
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There is a preview and P4C1026 download ( pdf file ) link at the bottom of this page. Total 10 Pages | ||
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P4C1026
ULTRA HIGH SPEED 256K x 4
STATIC CMOS RAM
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 15/20/25/35 ns (Commercial/Industrial)
– 20/25/35 ns (Military)
Low Power
www.DataSheet4U.Scoinmgle 5V±10% Power Supply
Data Retention with 2.0V Supply
Three-State Outputs
TTL/CMOS Compatible Outputs
Fully TTL Compatible Inputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil SOJ
– 28-Pin 400 mil SOJ
– 28-Pin 400 mil Ceramic DIP
– 32-Pin Ceramic LCC
DESCRIPTION
The P4C1026 is a 1 Meg ultra high speed static RAM
organized as 256K x 4. The CMOS memory requires no clock
or refreshing and has equal access and cycle times. Inputs
and outputs are fully TTL-compatible. The RAM operates
from a single 5V±10% tolerance power supply. With battery
backup, data integrity is maintained for supply voltages down
to 2.0V.
Access times as fast as 15 nanoseconds are available,
permitting greatly enhanced system speeds. CMOS is
utilized to reduce power consumption.
TheP4C1026is availableina28-pin300miland400milSOJ
packages, as well as Ceramic DIP and LCC packages,
providing excellent board level densities.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
SOJ (J5, J7), DIP (C7)
LCC(L13)
Document # SRAM127 REV E
Revised April 2007
1
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TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)(5,7)
P4C1026
AC CHARACTERISTICS - WRITE CYCLE
www.DataShee(t4VUC.Cco=m5V ± 10%, All Temperature Ranges)(2)
Sym. Parameter
tWC Write Cycle Time
tCW Chip Enable Time to End of Write
tAW Address Valid to End of Write
tAS Address Set-up Time
tWP Write Pulse Width
tAH Address Hold Time from End of Write
tDW Data Valid to End of Write
tDH Data Hold Time
tWZ Write Enable to Output in High Z
tDW Output Active from End of Write
-15 -20 -25 -35
Min Max Min Max Min Max Min Max
13 20 25 35
12 15 18 25
12 15 18 25
00 0 0
12 15 18 25
00 0 0
7 8 10 15
00 0 0
6 8 10 15
22
23
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(10,11)
Notes:
10. CE and WE must be LOW for WRITE cycle.
11. OE is LOW for this WRITE cycle to show tWZ and tOW.
12. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state
Document # SRAM127 REV E
13. Write Cycle Time is measured from the last valid address to the first
transitioning address.
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for P4C1026 electronic component. |
| Information | Total 10 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ P4C1026.PDF Datasheet ] | |
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