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PDF RT9005B Data sheet ( Hoja de datos )
| Número de pieza | RT9005B | |
| Descripción | (RT9005A / RT9005B) DDR VDDQ and Termination Voltage Regulator | |
| Fabricantes | Richtek Technology | |
| Logotipo |  |
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Preliminary
RT9005A/B
DDR VDDQ and Termination Voltage Regulator
General Description
The RT9005A/B is a dual-output linear regulator for DDR-
SDRAM VDDQ supply and termination voltage VTT supply.
The Regulator is capable of actively sinking or sourcing
up to 2A. The output termination voltage can be tightly
regulated to track 1/2 VDDQ by two external voltage divider
resistors.
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Ordering Information
RT9005
Package Type
SP : SOP-8 (Exposed Pad-Option 2)
Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commer-
cial Standard)
VOUT1 Output Voltage
A : 2.5V
B : 1.8V
Note :
Richtek Pb-free and Green products are :
`RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
`Suitable for use in SnPb or Pb-free soldering processes.
`100% matte tin (Sn) plating.
Features
z Ideal for DDR-I and DDR-II VDDQ, VTT Applications
z Integrated Power MOSFETs
z Generates Termination Voltage for SSTL_2,
SSTL _18, HSTL, SCSI-2 and SCSI-3 Interfaces
z High Accuracy Output Voltage at Full-Load
z VOUT2 Sink and Source 2A Continuous Current
z VOUT2 Adjustment by Two External Resistors
z Shutdown for Suspend to RAM (STR) Functionality
with High-Impedance Output
z Current Limiting Protection
z On-Chip Thermal Protection
z Available in SOP-8 (Exposed Pad) Packages
z RoHS Compliant and 100% Lead (Pb)-Free
Applications
z Desktop PCs, Notebooks, and Workstations
z Graphics Card Memory Termination
z Set Top Boxes, Digital TVs, Printers
z Embedded Systems
z Active Termination Buses
z DDR-I and DDR-II Memory Systems
Pin Configurations
(TOP VIEW)
BP
VIN1
VIN2
VCNTL
8
2
3
GND
9
7
6
45
VOUT1
GND
VOUT2
VREFEN
SOP-8 (Exposed Pad)
DS9005A/B-01 September 2007
www.richtek.com
1
1 page  
Preliminary
RT9005A/B
Parameter
Symbol
Test Conditions
Min Typ Max Units
Load Regulation (Note 7)
VOUT2 Current Limit
Protection
ΔVLOAD
ILIM2
IOUT = +2A
IOUT = −2A
−20 -- +20 mV
2.2 -- -- A
Thermal Shutdown Temperature TSD
Thermal Shutdown Hysteresis ΔTSD
REFEN Shutdown
Shutdown Threshold
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VIH
VIL
Enable
Shutdown
-- 170 --
-- 35 --
°C
°C
0.6 -- -- V
-- -- 0.2
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. θJA is measured in the natural convection at TA = 25°C on a high effective thermal conductivity test board (4 Layers,
2S2P) of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the expose pad for SOP-8 (Exposed
Pad) package.
Note 5. VOUT2 Standby current is the input current drawn by a regulator when the output voltage is disabled by a shutdown
signal on REFEN pin (VIL < 0.2V). It is measured with VIN2 = VCNTL = 5V.
Note 6. The dropout voltage is defined as VIN -VOUT, which is measured when VOUT is VOUT(NORMAL) − 100mV.
Note 7. Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load
regulation in the load range from 0A to 2A.
Note 8. VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN.
DS9005A/B-01 September 2007
www.richtek.com
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet RT9005B.PDF ] | |
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