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CYW15G0101DXB 데이터시트 PDF




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부품번호 CYW15G0101DXB 기능
기능 Single-channel HOTLink Transceiver
제조업체 Cypress Semiconductor
로고 Cypress Semiconductor 로고


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CYW15G0101DXB 데이터시트, 핀배열, 회로
CYP15G0101DXB
CYV15G0101DXB
CYW15G0101DXB
Single-channel HOTLink II™ Transceiver
Features
• Second-generation HOTLink® technology
• Compliant to multiple standards
— ESCON®, DVB-ASI, Fibre Channel and Gigabit
Ethernet (IEEE802.3z)
— CPRI™ compliant
www.DataSheet4U.coCmYW15G0101DXB compliant to OBSAI-RP3
— CYV15G0101DXB compliant to SMPTE 259M and
SMPTE 292M
— 8B/10B encoded or 10-bit unencoded data
• Single-channel transceiver operates from 195 to
1500 MBaud serial data rate
— CYW15G0101DXB operates from 195 to 1540 MBaud
• Selectable parity check/generate
• Selectable input clocking options
• Selectable output clocking options
• MultiFrame™ Receive Framer
— Bit and Byte alignment
— Comma or full K28.5 detect
— Single- or Multi-Byte framer for byte alignment
— Low-latency option
• Synchronous LVTTL parallel input and parallel output
interface
• Internal phase-locked loops (PLLs) with no external
PLL components
• Dual differential PECL-compatible serial inputs
— Internal DC-restoration
• Dual differential PECL-compatible serial outputs
Source matched for driving 50transmission lines
— No external bias resistors required
— Signaling-rate controlled edge-rates
• Optional Elasticity Buffer in Receive Path
• Optional Phase Align Buffer in Transmit Path
• Compatible with
— Fiber-optic modules
— Copper cables
— Circuit board traces
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Per-channel Link Quality Indicator
— Analog signal detect
— Digital signal detect
• Low power 1.25W @ 3.3V typical
• Single 3.3V supply
• 100-ball BGA
• Pb-Free package option available
0.25µ BiCMOS technology
Functional Description
The CYP(V)15G0101DXB[1] single-channel HOTLink II™
transceiver is a point-to-point communications building block
allowing the transfer of data over a high-speed serial link
(optical fiber, balanced, and unbalanced copper transmission
lines) at signaling speeds ranging from 195 to 1500 MBaud.
The transmit channel accepts parallel characters in an Input
Register, encodes each character for transport, and converts
it to serial data. The receive channel accepts serial data and
converts it to parallel data, frames the data to character bound-
aries, decodes the framed characters into data and special
characters, and presents these characters to an Output
Register. Figure 1 illustrates typical connections between
independent host systems and corresponding
CYP(V)(W)15G0101DXB parts. As a second-generation
HOTLink device, the CYP(V)(W)15G0101DXB extends the
HOTLink II family with enhanced levels of integration and
faster data rates, while maintaining serial-link compatibility
(data, command, and BIST) with other HOTLink devices.
10
10
Serial Link
Backplane or Cabled
Connections
10
10
Note:
Figure 1. HOTLink II System Connections
1. CYV15G0101DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYW15G0101DXB refers to OBSAI RP3 compliant devices (maximum
operating data rate is 1540 MBaud). CYP15G0101DXB refers to devices not compliant to SMPTE 259M and SMPTE 292M pathological test requirements and
also OBSAI RP3 operating datarate of 1536 MBaud. CYP(V)(W)15G0101DXB refers to all three devices.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-02031 Rev. *J
Revised March 24, 2005




CYW15G0101DXB pdf, 반도체, 판매, 대치품
CYP15G0101DXB
CYV15G0101DXB
CYW15G0101DXB
Pin Configuration
Top View
A
B
C
www.DataSheet4U.coDm
E
F
G
H
J
K
1
VCC
VCC
RFEN
2
IN2+
IN2–
LPEN
3
VCC
TDO
4567
OUT2– RXMODE TXMODE[1] IN1+
OUT2+ TXRATE TXMODE[0] IN1–
8
VCC
#NC[2]
9
OUT1–
OUT1+
10
VCC
VCC
RXLE RXCLKC+ RXRATE SDASEL SPDSEL PARCTL RFMODE INSEL
BOE[0] BOE[1] FRAMCHA
R
BISTLE DECMOD OELE
E
RXST[2] RXST[1] RXST[0]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TMS TRSTZ
TDI
TCLK RXCKSEL TXCKSEL
TXPER REFCLK– REFCLK+
RXOP
RXD[0]
VCC
VCC
RXD[1]
RXD[2]
RXD[3]
RXD[4]
RXD[5] GND
GND
GND
RXD[6]
LFI TXCT[1] TXD[6]
RXD[7] RXCLK– TXCT[0] TXD[5]
VCC RXCLK+ TXD[7] TXD[4]
Bottom View
GND
TXD[3]
TXD[2]
TXD[1]
TXOP TXCLKO+ TXCLKO–
TXCLK TXRST #NC[2]
TXD[0] #NC[2]
VCC
VCC
SCSEL
VCC
10 9
8
VCC
OUT1–
VCC
7
IN1+
654
TXMODE[1] RXMODE OUT2–
3
VCC
VCC OUT1+ #NC[2] IN1– TXMODE[0] TXRATE OUT2+ TDO
INSEL RFMODE PARCTL SPDSEL SDASEL RXRATE RXCLKC+ RXLE
2
IN2+
IN2–
LPEN
1
VCC
VCC
RFEN
TDI TRSTZ TMS
GND
TXCKSEL RXCKSEL TCLK
GND
REFCLK+ REFCLK– TXPER GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
FRAMCHA BOE[1] BOE[0]
R
OELE DECMOD BISTLE
E
RXST[0] RXST[1] RXST[2]
TXCLKO– TXCLKO+ TXOP
GND
GND
GND
GND RXD[5] RXD[1] RXOP
#NC[2] TXRST TXCLK TXD[3] TXD[6] TXCT[1]
LFI
RXD[6] RXD[2] RXD[0]
VCC
#NC[2] TXD[0]
VCC
SCSEL
VCC
Note:
2. #NC = Do Not Connect.
TXD[2]
TXD[1]
TXD[5] TXCT[0] RXCLK– RXD[7]
TXD[4] TXD[7] RXCLK+ VCC
RXD[3]
RXD[4]
VCC
VCC
A
B
C
D
E
F
G
H
J
K
Document #: 38-02031 Rev. *J
Page 4 of 39

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CYW15G0101DXB 전자부품, 판매, 대치품
CYP15G0101DXB
CYV15G0101DXB
CYW15G0101DXB
Pin Descriptions CYP(V)(W)15G0101DXB Single-channel HOTLink II (continued)
Pin Name I/O Characteristics Signal Description
Receive Path Data Signals
RXD[7:0]
LVTTL Output,
Parallel Data Output. These outputs change following the rising edge of the selected
synchronous to the receive interface clock.
RXCLKoutput
(or REFCLKinput[3]
when RXCKSEL =
LOW)
When the Decoder is enabled (DECMODE = HIGH or MID), these outputs represent either
received data or a special character. The status of the received data is represented by the
values of RXST[2:0].
When the Decoder is bypassed (DECMODE = LOW), RXD[7:0] become the higher order
bits of the 10-bit received character. See Table 13 for details.
RXST[2:0]
www.DataSheet4U.com
LVTTL Output,
Parallel Status Output. These outputs change following the rising edge of the selected
synchronous to the receive interface clock.
RXCLKoutput
(or REFCLKinput[3]
when RXCKSEL =
LOW)
When the Decoder is bypassed (DECMODE = LOW), RXST[1:0] become the two low-order
bits of the 10-bit received character, while RXST[2] = HIGH indicates the presence of a
Comma character in the Output Register.
When the Decoder is enabled (DECMODE = HIGH or MID), RXST[2:0] provide status of
the received signal. See Table 16 for a list of Receive Character status.
RXOP
3-state, LVTTL
Receive Path Odd Parity. When parity generation is enabled (PARCTL LOW), the parity
Output, synchronous output is valid for the data on the RXD bus bits.
to the RXCLK
output (or REFCLK
input[3] when
When parity
(High-Z).
generation
is
disabled
(PARCTL = LOW),
this
output
driver
is
disabled
RXCKSEL = LOW)
Receive Path Clock and Clock Control
RXCLK±
3-state, LVTTL
Output clock
Receive Character Clock Output. When configured such that the output data path is
clocked by the recovered clock (RXCKSEL = MID), these true and complement clocks are
the receive interface clocks which are used to control timing of output data (RXD[7:0],
RXST[2:0] and RXOP). This clock is output continuously at either the dual-character rate
(1/20th the serial bit-rate) or character rate (1/10th the serial bit-rate) of the data being
received, as selected by RXRATE.
When configured such that the output data path is clocked by REFCLK instead of recovered
clock (RXCKSEL = LOW), the RXCLK± output drivers present a buffered and delayed form
of REFCLK. In this mode, RXCLK± and RXCLKC+ are buffered forms of REFCLK that are
slightly different in phase, but follow the frequency and duty cycle of REFCLK. This phase
difference allows the user to select the optimal set-up/hold timing for their specific interface.
RXCLKC+ 3-state, LVTTL
Output
Delayed REFCLK+ when RXCKSEL = LOW. Delayed form of REFCLK+, used for transfer
of output data to a host system. This output is only enabled when the receive parallel
interface is configured to present data relative to REFCLK (RXCKSEL = LOW). When
RXCKSEL = LOW, the RXCLKC+ follows the frequency and duty cycle of REFCLK+.
RXRATE
LVTTL Input
Receive Clock Rate Select. When LOW, the RXCLK± recovered clock outputs are comple-
Static Control Input, mentary clocks operating at the recovered character rate. Data for the receive channel
internal pull-down should be latched on either the rising edge of RXCLK+ or falling edge of RXCLK–.
When HIGH, the RXCLK± recovered clock outputs are complementary clocks operating at
half the character rate. Data for the receive channel should be latched alternately on the
rising edge of RXCLK+ and RXCLK–.
When the output register is operated with REFCLK clocking (RXCKSEL = LOW), RXRATE
is not interpreted and RXCLK± follows the frequency and duty cycle of REFCLK.
RFEN
RXMODE
LVTTL input,
asynchronous,
internal pull-down
3-Level Select[4]
static control input
Reframe Enable. Active HIGH. When HIGH, the Framer in the receive channel is enabled
to frame per the presently enabled framing mode and selected framing character.
Receive Operating Mode. This input selects one of two RXST channel status reporting
modes and is only interpreted when the Decoder is enabled (DECMODE LOW). See
Table 12 for details.
Document #: 38-02031 Rev. *J
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부품번호상세설명 및 기능제조사
CYW15G0101DXB

Single-channel HOTLink Transceiver

Cypress Semiconductor
Cypress Semiconductor

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