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P2S28D40CTP 데이터시트 PDF




MIRA에서 제조한 전자 부품 P2S28D40CTP은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 P2S28D40CTP 자료 제공

부품번호 P2S28D40CTP 기능
기능 (P2S28D30CTP / P2S28D40CTP) 128M Double Data Rate Synchronous DRAM
제조업체 MIRA
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P2S28D40CTP 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



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P2S28D40CTP 데이터시트, 핀배열, 회로
Deutron Electronics Corp.
P2S28D30/40CTP
128M Double Data Rate Synchronous DRAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
P2S28D30CTP is a 4-bank x 4,194,304-word x 8bit,P2S28D40CTP is a 4-bank x 2,097,152-word x
16bit double data rate synchronous DRAM , with SSTL_2 interface. All control and address signals
www.DataSheet4U.com
are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe ,and
output data and data strobe are referenced on both edges of CLK. The P2S28D30/40CTP achieves
very high speed clock rate up to 200 MHz .
FEATURES
- Vdd=Vddq=2.5V+0.2V
- Double data rate architecture ; two data transfers per clock cycle.
- Bidirectional , data strobe (DQS) is transmitted/received with data
- Differential clock input (CLK and /CLK)
- DLL aligns DQ and DQS transitions with CLK transitions edges of DQS
- Commands entered on each positive CLK edge ;
- Data and data mask referenced to both edges of DQS
- 4 bank operation controlled by BA0 , BA1 (Bank Address)
- /CAS latency 2.0 / 2.5/ 3 (programmable) ;
Burst length - 2 / 4 / 8 (programmable)
Burst type - Sequential / Interleave (programmable)
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles / 64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-11 / Column address A0-9 , A0-9(x8) /A0-8(x16)
- SSTL_2 Interface
- Package
400-mil, 66-pin Thin Small Outline Package (TSOP II)
with 0.65mm lead pitch
- JEDEC standard for -6 , -75
- Intel standard for -5
DDR SDRAM (Rev.1.0)
Deutron Electronics Corp.
PDF created with pdfFactory Pro trial version www.pdffactory.com
1




P2S28D40CTP pdf, 반도체, 판매, 대치품
Deutron Electronics Corp.
P2S28D30/40CTP
128M Double Data Rate Synchronous DRAM
BLOCK DIAGRAM
P2S12D30ATP
DLL
www.DataSheet4U.com
DQ0 - 7
I/O Buffer
DQS
DQS Buffer
Memory
Array
Bank #0
Memory
Array
Bank #1
Memory
Array
Bank #2
Memory
Array
Bank #3
Mode Register
Control Circuitry
Address Buffer
A0-11 BA0,1
Clock Buffer
Control Signal Buffer
/CS /RAS /CAS /WE DM
CLK /CLK CKE
DDR SDRAM (Rev.1.0)
Deutron Electronics Corp.
PDF created with pdfFactory Pro trial version www.pdffactory.com
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P2S28D40CTP 전자부품, 판매, 대치품
COMMAND TRUTH TABLE
Deutron Electronics Corp.
P2S28D30/40CTP
128M Double Data Rate Synchronous DRAM
COMMAND
Deselect
No Operation
Row Address Entry &
www.DataSheet4U.cBomank Activate
Single Bank Precharge
Precharge All Banks
Column Address Entry
& Write
Column Address Entry
& Write with
Auto-Precharge
Column Address Entry
& Read
Column Address Entry
& Read with
Auto-Precharge
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
Burst Terminate
Mode Register Set
MNEMONIC CKE
n-1
DESEL
H
NOP
H
CKE
n
X
X
/CS
H
L
ACT
HHL
PRE
PREA
HHL
HHL
WRITE
HHL
WRITEA H H L
READ
HHL
READA
REFA
REFS
REFSX
TERM
MRS
HHL
HHL
HL L
L HH
L HL
HHL
HHL
/RAS /CAS /WE BA0,1 A10 A0-9, note
/AP 11
XXXXXX
HHHXXX
L HHVVV
L HL VL X
L HL XHX
HL L VL V
HL L VHV
HL HVL V
HL HVHV
L L HXXX
L L HXXX
XXXXXX
HHHXXX
H H L X X X1
L L L L L V2
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. Applies only to read bursts with autoprecharge disabled; this command is undefined (and should not be used) for
read bursts with autoprecharge enabled, and for write bursts.
2. BA0-BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register;BA0=1 ,
BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A11 provide the
op-code to be written to the selected Mode Register.
DDR SDRAM (Rev.1.0)
Deutron Electronics Corp.
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부품번호상세설명 및 기능제조사
P2S28D40CTP

(P2S28D30CTP / P2S28D40CTP) 128M Double Data Rate Synchronous DRAM

MIRA
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