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PDF ES25P80 Data sheet ( Hoja de datos )
| Número de pieza | ES25P80 | |
| Descripción | 8Mbit CMOS 3.0 Volt Flash Memory | |
| Fabricantes | Excel Semiconductor | |
| Logotipo |  |
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ADVANCED INFORMATION
EE SS II
Excel Semiconductor inc.
ES25P80
8Mbit CMOS 3.0 Volt Flash Memory
with 75Mhz SPI Bus Interface
www.DataSheet4U.com
ARCHITECTURAL ADVANTAGES
• Single power supply operation
- 2.7V -3.6V for read and program operations
• Memory Architecture
- Sixteen sectors with 512 Kb each
• Program
- Page program ( up to 256 bytes) in 1.5ms (typical)
- Program cycles are on a page by page basis
• Erase
- 0.5s typical sector erase time
- 6s typical bulk erase time
• Endurance
- 100,000 cycles per sector (typical)
• Data Retention
- 20 years (typical)
• Parameter Page
- 256 Byte page independent from main memory
for parameter storage
- Seperate from array, erase time < 20ms
• Device ID
- JEDEC standard two-byte electronic signature
- RES instruction one-byte electronic signature for
backward compatibility
- Manufacturer and device type ID
• Process Technology
- Manufactured on 0.18um process technology
• Package Option
- Industry Standard Pinouts
- 8-pin SO (208mil) package
- All Pb-Free devices are RoHS Compliant
PERFORMANCE CHARACTERISTICS
• Speed
- 75Mhz clock rate (maximum)
• Power Saving Standby Mode
- Standby mode 50uA (max)
- Deep Power Down Mode 1uA (typical)
MEMORY PROTECTION FEATURES
• Memory Protection
- W# pin works in conjunction with Status Register Bits
to protect specified memory areas
- Status Register Block Protection Bits (BP2, BP1, BP0)
in status register configure parts of memory as read
only
SOFTWARE FEATURES
• SPI Bus Compatible Serial Interface
ES25P80
1 Rev. 0D May, 11, 2006
1 page  
ADVANCED INFORMATION
EE SS II
Excel Semiconductor inc.
SPI Interface with
(CPOL, CPHA) =
(0,0) or (1,1)
Bus Master
www.DataSheet4U.com
SO
SI
SCK
SCK SO
SI
SPI Memory
Device
SCK SO SI
SPI Memory
Device
SCK SO SI
SPI Memory
Device
CS1 CS2 CS3
CS# W# HOLD# CS# W# HOLD# CS# W# HOLD#
Figure 1. Bus Master and Memory Devices on the SPI Bus
Note : The Write Protect (W#) and Hold (HOLD#) signals should be driven, High or Low as appropriate
CS#
CPOL CPHA
0 0 SCK
1 1 SCK
SI
SO
MSB
MSB
Figure 2. SPI Modes Supported
ES25P80
5 Rev. 0D May, 11, 2006
5 Page 
ADVANCED INFORMATION
EE SS II
Excel Semiconductor inc.
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 4) sets
the Write Enable Latch (WEL) bit. The Write Enable
Latch (WEL) bit must be set prior to every Page Pro-
gram (PP or PPP), Erase (SE, BE or PE) and Write
Status Register (WRSR) instruction. The Write
Enable (WREN) instruction is entered by driving
Chip Select (CS#) Low, sending the instruction code,
www.DataSheet4aUn.dcotmhen driving Chip Select (CS#) High.
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 5)
resets the Write Enable Latch (WEL) bit. The Write
Disable (WRDI) instruction is entered by driving Chip
Select (CS#) Low, sending the instruction code, and
then driving Chip Select (CS#) High.
The Write Enable (WEL) bit is reset under the follow-
ing conditions :
- Power-up
- WRDI instruction completion
- WRSR instruction completion
- PP instruction completion
- SE instruction completion
- BE instruction completion
CS#
SCK
SI
SO
01
2 3 4 56 7
00
Instruction
0 0 0 11 0
High Impedance
Figure 4. Write Enable ( WREN ) Instruction Sequence
CS#
SCK
SI
SO
0
12
3 4 567
00
Instruction
0 0 0 10 0
High Impedance
Figure 5. Write Disable ( WRDI ) Instruction Sequence
ES25P80
11 Rev. 0D May, 11, 2006
11 Page | ||
| Páginas | Total 35 Páginas | |
| PDF Descargar | [ Datasheet ES25P80.PDF ] | |
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