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WM8213 데이터시트 PDF




Wolfson Microelectronics에서 제조한 전자 부품 WM8213은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 WM8213 기능
기능 24MSPS 16-bit CCD Digitiser
제조업체 Wolfson Microelectronics
로고 Wolfson Microelectronics 로고


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WM8213 데이터시트, 핀배열, 회로
w
24MSPS 16-bit CCD Digitiser
WM8213
DESCRIPTION
The WM8213 is a 16-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals
from CCD sensors or Contact Image Sensors (CIS) at pixel
www.DataSheet4U.scaommple rates of up to 24MSPS.
The device includes three analogue signal processing
channels each of which contains Reset Level Clamping,
Correlated Double Sampling and Programmable Gain and
Offset adjust functions. Three multiplexers allow single
channel processing. The output from each of these
channels is time multiplexed into a single high-speed 16-bit
Analogue to Digital Converter. The digital output data is
available in 8-bit wide multiplexed format and there is also
an optional single byte output mode, or 4-bit multiplexed
LEGACY mode.
An internal 4-bit DAC is supplied for internal reference level
generation. This may be used during CDS to reference CIS
signals or during Reset Level Clamping to clamp CCD
signals. An external reference level may also be supplied.
ADC references are generated internally, ensuring optimum
performance from the device.
Using an analogue supply voltage of 3.3V and a digital
interface supply of 3.3V, the WM8213 typically only
consumes 350mW.
BLOCK DIAGRAM
FEATURES
16-bit ADC
24MSPS conversion rate
Low power – 350mW typical
3.3V single supply operation
Single, 2 or 3 channel operation
Correlated double sampling
Programmable gain (9-bit resolution)
Programmable offset adjust (8-bit resolution)
Flexible clamp control with programmable clamp voltage
Flexible timing, can be made compatible with WM819X
and WM815X parts.
8-bit wide multiplexed data output format
8-bit only output mode
4-bit LEGACY multiplexed nibble mode
Internally generated voltage references
28-lead SSOP package, pin compatible with WM8199
Serial control interface
APPLICATIONS
High speed USB2.0 compatible scanners
Multi-function peripherals
High-performance CCD sensor interface
Digital Copiers
WOLFSON MICROELECTRONICS plc
To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/
Production Data, July 2007, Rev 4.0
Copyright ©2007 Wolfson Microelectronics plc.




WM8213 pdf, 반도체, 판매, 대치품
WM8213
Production Data
PIN DESCRIPTION
PIN
1
2
3
4
5
6
7
www.DataSheet4U.com8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NAME
RINP
AGND2
DVDD1
OEB
VSMP
RSMP
MCLK
DGND
SEN
DVDD2
SDI
SCK
TYPE
Analogue input
Supply
Supply
Digital input
Digital input
Digital input
Digital input
Supply
Digital input
Supply
Digital input
Digital input
OP[0]
OP[1]
OP[2]
OP[3]
OP[4]
OP[5]
OP[6]
OP[7]/SDO
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
AVDD
AGND1
VRB
Supply
Supply
Analogue output
VRT
Analogue output
VRX
Analogue output
VRLC/VBIAS Analogue I/O
BINP
GINP
Analogue input
Analogue input
DESCRIPTION
Red channel input video.
Analogue ground reference.
Digital supply for logic and clock generator. This must be operated at the same
potential as AVDD.
Output Hi-Z control, all digital outputs disabled when register bit OEB = 1 or register
bit OPD = 1.
Video sample timing pulse.
Reset sample timing pulse (also used for RLC control).
Master (ADC) clock. This determines the ADC conversion rate.
Digital ground reference.
Enables the serial interface when high.
Digital supply, all digital I/O pins.
Serial data input.
Serial clock.
Digital multiplexed output data bus.
ADC output data (d15:d0) is available in multiplexed format as shown. See ‘Output
Formats’ description in Device Description section for details of other output modes.
AB
d8 d0
d9 d1
d10 d2
d11 d3
d12 d4
d13 d5
d14 d6
d15 d7
Alternatively, pin OP[7]/SDO may be used to output register read-back data when
register bit OEB = 0, OPD = 0 and SEN has been pulsed high. See Serial Interface
description in Device Description section for further details.
Analogue supply. This must be operated at the same potential as DVDD1.
Analogue ground reference.
Lower reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
Upper reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
Input return bias voltage.
This pin must be connected to AGND via a decoupling capacitor.
Selectable analogue output voltage for RLC or single-ended bias reference.
This pin would typically be connected to AGND via a decoupling capacitor.
VRLC can be externally driven if programmed Hi-Z.
Blue channel input video.
Green channel input video.
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PD Rev 4.0 July 2007
4

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WM8213 전자부품, 판매, 대치품
Production Data
WM8213
Test Conditions
AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25°C, MCLK = 24MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
MIN TYP MAX
CONDITIONS
Reset-Level Clamp (RLC) circuit/ Reference Level DAC
RLC switching impedance
50
VRLC short-circuit current
2
VRLC output resistance
2
VRLC Hi-Z leakage current
VRLC = 0 to AVDD
1
Reference RLCDAC resolution
4
Reference RLCDAC step size
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VRLCSTEP
AVDD=3.3V
RLCDACRNG=0
0.173
Reference RLCDAC step size
Reference RLCDAC output
voltage at code 0(hex)
VRLCSTEP
VRLCBOT
RLCDACRNG=1
AVDD=3.3V,
RLCDACRNG=0
0.11
0.4
Reference RLCDAC output
voltage at code 0(hex)
VRLCBOT
RLCDACRNG=1
0.4
Reference RLCLDAC output
voltage at code F(hex)
VRLCTOP
AVDD=3.3V,
RLCDACRNG=0
3.0
Reference RLCDAC output
voltage at code F(hex)
VRLCTOP
RLCDACRNG = 1
2.05
RLCDAC
DNL
-0.5 +0.5
RLCDAC
INL
+/-1
Offset DAC, Monotonicity Guaranteed
Resolution
Differential non-linearity
DNL
Integral non-linearity
INL
Step size
Output voltage
Programmable Gain Amplifier
Resolution
Gain equation
Max gain, each channel
Min gain, each channel
Channel Matching
Analogue to Digital Converter
Resolution
Speed
Full-scale input range
(2*(VRT-VRB))
GMAX
GMIN
Code 00(hex)
Code FF(hex)
LOWREFS=0
LOWREFS=1
8
0.1
0.25
2.04
-260
+260
0.5
1
9
0.66
+
7.34
511
*
PGA[ 8
:
0]
8
0.66
1
5
16
24
2
1.2
UNIT
mA
µA
bits
V/step
V/step
V
V
V
V
LSB
LSB
bits
LSB
LSB
mV/step
mV
mV
bits
V/V
V/V
V/V
%
bits
MSPS
V
V
w
PD Rev 4.0 July 2007
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