|
|
PDF N2DS12H16CT Data sheet ( Hoja de datos )
| Número de pieza | N2DS12H16CT | |
| Descripción | 128Mb DDR SDRAM | |
| Fabricantes | Elixir | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de N2DS12H16CT (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
N2DS12H16CT
128Mb DDR SDRAM
Features
CAS Latency and Frequency
CAS
Latency
Maximum Operating Frequency (MHz)*
DDR400
(-5/-5T)
DDR333
(-6K)*
DDR266B
(-75B)
2.5 166 133 100
3 200 166 133
* -6K also meets DDR266A Spec (MHz-CL-tRCD-tRP = 133-2.5-3-3)
• Double data rate architecture: two data transfers per
clock cycle
• Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver
• DQS is edge-aligned with data for reads and is center-
aligned with data for writes
• Differential clock inputs (CK and CK)
www.DataSheet4U.com
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
• Burst lengths: 2, 4, or 8
• CAS Latency: 2 / 2.5(DDR333), 2.5 / 3(DDR400)
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 7.8µs Maximum Average Periodic Refresh Interval
• 2.5V (SSTL_2 compatible) I/O
• VDDQ = VDD = 2.6V ± 0.1V(DDR400)
• VDDQ = VDD = 2.5V ± 0.2V (DDR333)
• -5/-5T Speed sort; Support PC3200/2700/2100 modules
• -6K Speed sort: Supports PC2700/PC2100 modules
• -75B Speed sort: Supports PC2100 modules
Description
The 128Mb DDR SDRAM is a high-speed CMOS, dynamic
random-access memory containing 134,217,728 bits. It is
internally configured as a quad-bank DRAM.
The 128Mb DDR SDRAM uses a double-data-rate architec-
ture to achieve high-speed operation. The double data rate
architecture is essentially a 2n prefetch architecture with an
interface designed to transfer two data words per clock cycle
at the I/O pins. A single read or write access for the 128Mb
DDR SDRAM effectively consists of a single 2n-bit wide, one
clock cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQS is edge-
aligned with data for Reads and center-aligned with data for
Writes.
The 128Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write com-
mand. The address bits registered coincident with the Active
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4, or 8 locations. An Auto Precharge func-
tion may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst access.
As with standard SDRAMs, the pipelined, multibank architec-
ture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row pre-
charge and activation time.
An auto refresh mode is provided along with a power-saving
Power Down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II com-
patible.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode
of operation.
REV 0.2
02/2004
1
1 page  
N2DS12H16CT
128Mb DDR SDRAM
Block Diagram (8Mb x 16)
CKE
CK
CK
CS
WE
CAS
RAS
Mode
Registers
15 13
www.DataSheet4U.com
A0-A12,
BA0, BA1
15
2
13
2
9
Column-Address
Counter/Latch
Bank1 Bank2 Bank3
CK, CK
DLL
8192
Bank0
Memory
Array
(8192 x 256 x 32)
Sense Amplifiers
I/O Gating
DM Mask Logic
(2x3526)
Column
Decoder
8
COL0
1
32
32
32
Data
16
16
16
DQS
1
Generator
COL0 Input
Register
Write Mask 1
1
FIFO
&
Drivers
21
32 16
oclukt cinlk Data 16
1
16
16
DQS
1
16
CK, COL0
CK
1
DQ0-DQ15,
LDM, UDM
LDQS,UDQS
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
REV 0.2
02/2004
5
5 Page 
N2DS12H16CT
128Mb DDR SDRAM
Extended Mode Register
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions
include DLL enable/disable, bit A0; output drive strength selection, bit A1; and QFC output enable/disable, bit A2. These func-
tions are controlled via the bit settings shown in the Extended Mode Register Definition. The Extended Mode Register is pro-
grammed via the Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored information until it is
programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are idle, and the
controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements result in
unspecified operation.
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to nor-
mal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically disabled when
entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled,
200 clock cycles must occur to allow time for the internal clock to lock to the externally applied clock before a Read command
can be issued. This is the reason for introducing timing parameter tXSRD for DDR SDRAM’s (Exit Self Refresh to Read Com-
www.DatamthSaehnDdeL)e.LNt4isoUne-n.cRaobemlaeddcvoiamsmealfnrdesfrecashn
be issued 2 clocks after the DLL is enabled via the EMRS command
exit command (tXSNR, Exit Self Refresh to Non-Read Command).
(tMRD)
or
10
clocks
after
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II.
QFC Enable/Disable
The QFC signal is an optional DRAM output control used to isolate module loads (DIMMs) from the system memory bus by
means of external FET switches when the given module (DIMM) is not being accessed. The QFC function is an optional feature
for “elixie” and is not included on all DDR SDRAM devices.
REV 0.2
02/2004
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet N2DS12H16CT.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| N2DS12H16CT | 128Mb DDR SDRAM | Elixir |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |