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AD9984A 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD9984A은 전자 산업 및 응용 분야에서
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부품번호 AD9984A 기능
기능 High Performance 10-Bit Display Interface
제조업체 Analog Devices
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AD9984A 데이터시트, 핀배열, 회로
FEATURES
10-bit, analog-to-digital converters
170 MSPS maximum conversion rate
Low PLL clock jitter at 170 MSPS
Automatic gain matching
Automated offset adjustment
2:1 input mux
www.DataSheePt4oUw.ceorm-down via dedicated pin or serial register
4:4:4, 4:2:2, and DDR output format modes
Variable output drive strength
Odd/even field detection
External clock input
Regenerated Hsync output
Programmable output high impedance control
Hsyncs per Vsync counter
Sync-on-green (SOG) pulse filter
Pb-free package
APPLICATIONS
Advanced TVs
Plasma display panels
LCDTV
HDTV
RGB graphics processing
LCD monitors and projectors
Scan converters
GENERAL DESCRIPTION
The AD9984A is a complete 10-bit, 170 MSPS, monolithic
analog interface optimized for capturing YPbPr video and RGB
graphics signals. Its 170 MSPS encode rate capability and full
power analog bandwidth of 300 MHz support all HDTV video
modes up to 1080p, as well as graphics resolutions up to UXGA
(1600 × 1200 at 60 Hz).
The AD9984A includes a 170 MHz triple ADC with an internal
reference, a PLL, and programmable gain, offset, and clamp
control. The user provides only a 1.8 V power supply and an
analog input. Three-state CMOS outputs can be powered from
1.8 V to 3.3 V.
The AD9984A on-chip PLL generates a sample clock from the
tri-level sync (for YPbPr video) or the horizontal sync (for RGB
graphics). Sample clock output frequencies range from 10 MHz
to 170 MHz. With internal coast generation, the PLL maintains
its output frequency in the absence of a sync input. A 32-step
High Performance
10-Bit Display Interface
AD9984A
FUNCTIONAL BLOCK DIAGRAM
AD9984A
10 AUTO OFFSET
Pr/REDIN1
Pr/REDIN0
2:1
MUX
AUTO GAIN
CLAMP
PGA
10-BIT
ADC
10 AUTO OFFSET
Y/GREENIN1
Y/GREENIN0
2:1
MUX
AUTO GAIN
CLAMP
PGA
10-BIT
ADC
10 AUTO OFFSET
Pb/BLUEIN1
Pb/BLUEIN0
2:1
MUX
CLAMP
AUTO GAIN
PGA
10-BIT
ADC
10 Cb/Cr/REDOUT
10
Y/GREENOUT
10
Cb/BLUEOUT
HSYNC1
HSYNC0
VSYNC0
VSYNC1
SOGIN1
SOGIN0
EXTCK/COAST
CLAMP
FILT
SDA
SCL
2:1
MUX
2:1
MUX
2:1
MUX
SYNC
PROCESSING
PLL
POWER
MANAGEMENT
SERIAL REGISTER
Figure 1.
DATACK
SOGOUT
ODD/EVEN FIELD
HSOUT
VSOUT/A0
VOLTAGE
REFS
REFHI
REFLO
sampling clock phase adjustment is provided. Output data,
sync, and clock phase relationships are maintained.
The auto-offset feature can be enabled to automatically restore
the signal reference levels and calibrate out any offset differences
between the three channels. The auto channel-to-channel gain-
matching feature can be enabled to minimize any gain
mismatches between the three channels.
The AD9984A also offers full sync processing for composite sync
and sync-on-green applications. A clamp signal is generated
internally or can be provided by the user through the CLAMP
input pin.
Fabricated in an advanced CMOS process, the AD9984A is
provided in a space-saving, Pb-free, 80-lead low profile quad
flat package (LQFP) or 64-lead lead frame chip scale package
(LFCSP) and is specified over the 0°C to 70°C temperature range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.




AD9984A pdf, 반도체, 판매, 대치품
AD9984A
Parameter
POWER SUPPLY
VD Supply Voltage
VDD Supply Voltage
PVD Supply Voltage
DAVDD Supply Voltage
VD Supply Current (ID)
VDD Supply Current (IDD)
PVD Supply Current (IPVD)
DAVDD Supply Current (IDAVDD)
www.DataShTeoetta4lUP.ocowmer Dissipation
Power-Down Supply Current
Power-Down Dissipation
DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power
Crosstalk
Temp
Full
Full
Full
Full
25°C
25°C
25°C
25°C
Full
Full
Full
25°C
Full
Test
Level1
IV
IV
IV
IV
V
V
V
V
VI
VI
VI
V
V
AD9984AKSTZ-140
AD9984AKCPZ-140
Min Typ Max
1.7 1.8 1.9
1.7 3.3 3.47
1.7 1.8 1.9
1.7 1.8 1.9
250
31
9
16
710
10
18
300
60
1 See the Explanation of Test Levels section.
2 Guaranteed by design, not production tested.
AD9984AKSTZ-170
AD9984AKCPZ-170
Min Typ Max
1.755 1.8
1.9
1.7 3.3 3.47
1.7 1.8 1.9
1.7 1.8 1.9
255
34
9
19
740
10
18
300
60
Unit
V
V
V
V
mA
mA
mA
mA
mW
mA
mW
MHz
dBc
Rev. 0 | Page 4 of 44

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AD9984A 전자부품, 판매, 대치품
www.DataSheet4U.com
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GREEN 9 1
GREEN 8 2
GREEN 7 3
GREEN 6 4
GREEN 5 5
GREEN 4 6
GREEN 3 7
GREEN 2 8
GREEN 1 9
GREEN 0 10
BLUE 9 11
BLUE 8 12
BLUE 7 13
BLUE 6 14
BLUE 5 15
BLUE 4 16
PIN 1
INDICATOR
AD9984A
TOP VIEW
(Not to Scale)
48 O/E FIELD
47 REFHI
46 REFLO
45 PWRDN
44 RAIN1
43 RAIN0
42 VD
41 SOGIN1
40 GAIN1
39 VD
38 SOGIN0
37 GAIN0
36 VD
35 BAIN1
34 BAIN0
33 VD
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 3. 64-Lead LFCSP Pin Configuration
Table 4. Complete Pin Configuration List
Pin Number
Pin Type
80-Lead LQFP 64-Lead LFCSP
Inputs
14
43
16 44
6 37
10 40
2 34
4 35
70 26
68 24
71 27
69 25
8 38
12 41
72 28
73 29
72 28
17 45
Mnemonic
RAIN0
RAIN1
GAIN0
GAIN1
BBAIN0
BBAIN1
HSYNC0
HSYNC1
VSYNC0
VSYNC1
SOGIN0
SOGIN1
EXTCK1
CLAMP
COAST1
PWRDN
Function
Channel 0 Analog Input for Converter R
Channel 1 Analog Input for Converter R
Channel 0 Analog Input for Converter G
Channel 1 Analog Input for Converter G
Channel 0 Analog Input for Converter B
Channel 1 Analog Input for Converter B
Horizontal Sync Input for Channel 0
Horizontal Sync Input for Channel 1
Vertical Sync Input for Channel 0
Vertical Sync Input for Channel 1
Input for Sync-on-Green Channel 0
Input for Sync-on-Green Channel 1
External Clock Input
External Clamp Input Signal
External PLL Coast Signal Input
Power-Down Control
AD9984A
Value
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
0.0 V to 1.0 V
0.0 V to 1.0 V
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
Rev. 0 | Page 7 of 44

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AD9984A

High Performance 10-Bit Display Interface

Analog Devices
Analog Devices

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