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17S50A PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 17S50A
기능 Spartan-II/Spartan-IIE Family OTP Configuration PROMs
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17S50A 데이터시트, 핀배열, 회로
0
R
DS078 (v1.8) November 18, 2002
05
Features
• Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams for
Spartan-II/Spartan-IIE FPGA devices
• Simple interface to the Spartan device
• Programmable reset polarity (active High or active
Low)
• Low-power CMOS floating gate process
www.DataShee3t4.3UV.coPmROM
Spartan-II/Spartan-IIE Family
OTP Configuration PROMs
(XC17S00A)
Advance Product Specification
• Available in compact plastic 8-pin DIP, 8-pin VOIC,
20-pin SOIC, or 44-pin VQFP packages.
• Programming support by leading programmer
manufacturers.
• Design support using the Xilinx Alliance and
Foundation series software packages.
• Guaranteed 20-year life data retention
Introduction
The XC17S00A family of PROMs provide an easy-to-use,
cost-effective method for storing Spartan-II/Spartan-IIE
device configuration bitstreams.
When the Spartan device is in Master Serial mode, it
generates a configuration clock that drives the Spartan
PROM. A short access time after the rising clock edge, data
appears on the PROM DATA output pin that is connected to
the Spartan device DIN pin. The Spartan device generates
the appropriate number of clock pulses to complete the
configuration. Once configured, it disables the PROM.
When a Spartan device is in Slave Serial mode, the PROM
and the Spartan device must both be clocked by an
incoming signal.
For device programming, either the Xilinx Alliance or the
Spartan device design file into a standard HEX format
which is then transferred to most commercial PROM
programmers.
Spartan-II/IIE FPGA
Configuration Bits
Compatible Spartan-II/IIE PROM
XC2S15
197,696
XC17S15A
XC2S30
336,768
XC17S30A
XC2S50
559,200
XC17S50A
XC2S100
781,216
XC17S100A
XC2S150
1,040,096
XC17S150A
XC2S200
1,335,840
XC17S200A
XC2S50E
630,048
XC17S50A
XC2S100E
XC2S150E(1)
863,840
1,134,496
XC17S100A
XC17S200A
XC2S200E
1,442,016
XC17S200A
XC2S300E
XC2S400E
XC2S600E
1,875,648
2,693,440
3,961,632
XC17S300A
XC17V04(2)
XC17V04(2)
Notes:
1. Due to the higher configuration bit requirements of the XC2S150E device, an XC17S200A PROM is required to configure this FPGA.
2. See XC17V00 series configuration PROMs data sheet at: http://direct.xilinx.com/bvdocs/publications/ds073.pdf
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other
trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature,
application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may
require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties
or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
DS078 (v1.8) November 18, 2002
Advance Product Specification
www.xilinx.com
1-800-255-7778
1




17S50A pdf, 반도체, 판매, 대치품
Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
R
www.DataSheet4U.com
Spartan-II/
Spartan-IIE
Master Serial
M0
M1
M2
DIN
CCLK
DONE
INIT
3.3V
3.3V
3.3K
3.3K
VCC
VCC
DATA
CLK XC17S00A
CE PROM
OE/RESET
Notes:
1. If the DriveDone configuration option is not active, pull up DONE with a 3.3kresistor.
(Low Resets the Address Pointer)
CCLK
(Output)
DIN
DOUT
(Output)
DS078_01_110601
Figure 1: Master Serial Mode
The one-time-programmable XC17S00A PROM in Figure 1 early DONE inhibits the PROM data output one CCLK cycle
supports automatic loading of configuration programs. An before the Spartan FPGA I/Os become active.
4
www.xilinx.com
DS078 (v1.8) November 18, 2002
1-800-255-7778
Advance Product Specification

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17S50A 전자부품, 판매, 대치품
R Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
AC Characteristics Over Operating Condition(1)
CE
ESET/OE
CLK
DATA
www.DataSheet4U.com
TSCE
TOE
TCE
TLC THC
TCAC
TCEH
TSCE
TCYC
TOH
TDF
TOH
THCE
THOE
DS030_03_111502
Symbol
Description
Min Max
TOE RESET/OE to Data Delay
- 45
TCE CE to Data Delay
- 60
TCAC
TOH
TDF
CLK to Data Delay
Data Hold From CE, RESET/OE, or CLK(2)
CE or RESET/OE to Data Float Delay(2,3)
- 80
0-
- 50
TCYC
TLC
THC
Clock Periods
CLK Low Time(2)
CLK High Time(2)
100 -
50 -
50 -
TSCE
CE Setup Time to CLK (to guarantee proper counting)
25 -
THCE
CE Hold Time to CLK (to guarantee proper counting)
0-
THOE
RESET/OE Hold Time (guarantees counters are reset)
25 -
TCEH
CE High time (guarantees counters are reset)
20 -
Notes:
1. AC test load = 50 pF
2. Guaranteed by design, not tested.
3. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
5. If TCEH High < 2µs, TCE = 2 µs.
6. If THOE High < 2µs, TCE = 2 µs.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS078 (v1.8) November 18, 2002
Advance Product Specification
www.xilinx.com
1-800-255-7778
7

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17S50A

Spartan-II/Spartan-IIE Family OTP Configuration PROMs

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