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부품번호 | ATINY26 기능 |
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기능 | 8-Bit Microcontroller | ||
제조업체 | ATMEL Corporation | ||
로고 | |||
Features
• High-performance, Low-power AVR ® 8-bit Microcontroller
• RISC Architecture
– 118 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
• Data and Non-volatile Program Memory
– 2K Bytes of In-System Programmable Program Memory Flash
Endurance: 10,000 Write/Erase Cycles
– 128 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– 128 Bytes Internal SRAM
– Programming Lock for Flash Program and EEPROM Data Security
www.Data•ShPeeetr4ipUh.ceormal Features
– 8-bit Timer/Counter with Separate Prescaler
– 8-bit High-speed Timer with Separate Prescaler
2 High Frequency PWM Outputs with Separate Output Compare Registers
Non-overlapping Inverted PWM Output Pins
– Universal Serial Interface with Start Condition Detector
– 10-bit ADC
11 Single Ended Channels
8 Differential ADC Channels
7 Differential ADC Channel Pairs with Programmable Gain (1x, 20x)
– On-chip Analog Comparator
– External Interrupt
– Pin Change Interrupt on 11 Pins
– Programmable Watchdog Timer with Separate On-chip Oscillator
• Special Microcontroller Features
– Low Power Idle, Noise Reduction, and Power-down Modes
– Power-on Reset and Programmable Brown-out Detection
– External and Internal Interrupt Sources
– In-System Programmable via SPI Port
– Internal Calibrated RC Oscillator
• I/O and Packages
– 20-lead PDIP/SOIC: 16 Programmable I/O Lines
• Operating Voltages
– 2.7V - 5.5V for ATtiny26L
– 4.5V - 5.5V for ATtiny26
• Speed Grades
– 0 - 8 MHz for ATtiny26L
– 0 - 16 MHz for ATtiny26
8-bit
Microcontroller
with 2K Bytes
Flash
ATtiny26
ATtiny26L
Preliminary
Rev. 1477D–AVR–06/03
1
Block Diagram
www.DataSheet4U.com
Figure 1. The ATtiny26(L) Block Diagram
VCC
GND
PROGRAM
COUNTER
8-BIT DATA BUS
INTERNAL
OSCILLATOR
STACK
POINTER
WATCHDOG
TIMER
AVCC
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
SRAM
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
STATUS
REGISTER
MCU CONTROL
REGISTER
MCU STATUS
REGISTER
TIMER/
COUNTER0
TIMER/
COUNTER1
UNIVERSAL
SERIAL
INTERFACE
INTERRUPT
UNIT
PROGRAMMING
LOGIC
ISP INTERFACE
EEPROM
INTERNAL
CALIBRATED
OSCILLATOR
TIMING AND
CONTROL
OSCILLATORS
DATA REGISTER
PORT A
DATA DIR.
REG.PORT A
ADC
DATA REGISTER
PORT B
DATA DIR.
REG.PORT B
PORT A DRIVERS
PORT B DRIVERS
PA0-PA7
PB0-PB7
4 ATtiny26(L)
1477D–AVR–06/03
4페이지 www.DataSheet4U.com
General Purpose
Register File
ATtiny26(L)
pipelining. While one instruction is being executed, the next instruction is pre-fetched
from the program memory. This concept enables instructions to be executed in every
clock cycle. The program memory is In-System programmable Flash memory.
With the relative jump and relative call instructions, the whole address space is directly
accessed. All AVR instructions have a single 16-bit word format, meaning that every
program memory address contains a single 16-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is
stored on the Stack. The Stack is effectively allocated in the general data SRAM, and
consequently the stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the reset routine (before subroutines
or interrupts are executed). The 8-bit Stack Pointer SP is read/write accessible in the I/O
space. For programs written in C, the stack size must be declared in the linker file. Refer
to the C user guide for more information.
The 128 bytes data SRAM can be easily accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control
Registers, Timer/Counters, and other I/O functions. The memory spaces in the AVR
architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional
Global Interrupt Enable bit in the Status Register. All the different interrupts have a sep-
arate Interrupt Vector in the Interrupt Vector table at the beginning of the program
memory. The different interrupts have priority in accordance with their Interrupt Vector
position. The lower the Interrupt Vector address, the higher the priority.
Figure 3 shows the structure of the 32 general purpose working registers in the CPU.
Figure 3. AVR CPU General Purpose Working Registers
General
Purpose
Working
Registers
70
R0
R1
R2
…
R13
R14
R15
R16
R17
…
R26
R27
R28
R29
R30
R31
Addr.
$00
$01
$02
$0D
$0E
$0F
$10
$11
$1A
$1B
$1C
$1D
$1E
$1F
X-register Low Byte
X-register High Byte
Y-register Low Byte
Y-register High Byte
Z-register Low Byte
Z-register High Byte
1477D–AVR–06/03
7
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부품번호 | 상세설명 및 기능 | 제조사 |
ATINY26 | 8-Bit Microcontroller | ATMEL Corporation |
ATINY26L | 8-Bit Microcontroller | ATMEL Corporation |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |