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PDF EMC646SP16J Data sheet ( Hoja de datos )
| Número de pieza | EMC646SP16J | |
| Descripción | 4Mx16 bit CellularRAM | |
| Fabricantes | EMLSI | |
| Logotipo |  |
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Document Title
4Mx16 bit CellularRAM
Revision History
www.DataRSehveiest4ioUn.cNomo. History
0.0 Initial Draft
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Draft Date
July 05,2007
Remark
Preliminary
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : 690-717
Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to
your questions about device. If you have any questions, please contact the EMLSI office.
1
1 page  
Preliminary
EMC646SP16J
4Mx16 CellularRAM
List of Tables
Table 1: PIN Descriptions .......................................................................................................................................................... 7
Table 2: Bus Operations ............................................................................................................................................................ 8
Table 3: Sequence and Burst Length ........................................................................................................................................ 23
Table 4: Drive Strength .............................................................................................................................................................. 24
Table 5: Variable Latency Configuration Codes......................................................................................................................... 25
Table 6: Fixed Latency Configuration Codes............................................................................................................................. 26
www.DatTaaSbhleee7t4:U.coAmddress Patterns for PAR(RCR[4] =1)......................................................................................................................... 28
Table 8: Device Identification Register Mapping ....................................................................................................................... 28
Table 9: Absolute Maximum Ratings ......................................................................................................................................... 29
Table 10: Electrical Characteristics and Operating Conditions .................................................................................................... 29
Table 11: Deep Power-Down Specifications ............................................................................................................................... 30
Table 12: Capacitance ................................................................................................................................................................ 30
Table 13: Asynchronous READ Cycle Timing Requirements ...................................................................................................... 31
Table 14: Burst READ Cycle Timing Requirements .................................................................................................................... 32
Table 15: Asynchronous WRITE Cycle Timing Requirements .................................................................................................... 33
Table 16: Burst WRITE Cycle Timing Requirements ................................................................................................................... 34
Table 17: Initialization and DPD Timing Parameters ................................................................................................................... 35
5
5 Page 
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Figure 4: WRITE Operation (ADV# LOW)
www.DataSheet4U.com
CE#
OE#
WE#
Address
< tCEM
Address Valid
DATA
High-Z
Data Valid
LB#/UB#
tWC = WRITE Cycle Time
Don’t Care
Page Mode Read Operation
Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In page-mode-capable products, an
initial asynchronous read access is performed, then adjacent addresses can be read quickly by simply changing the low-order address.
Addresses A[3:0] are used to determine the members of the 16-address CellularRAM page. Any change in addresses A[4] or higher will
initiate a new tAA access time. Figure 5 shows the timing for a page mode access. Page mode takes advantage of the fact that adjacent
addresses can be read in a shorter period of time than random addresses. WRITE operations do not include comparable page mode
functionality. During asynchronous page mode operation, the CLK input must be held LOW. CE# must be driven HIGH upon completion
of a page mode access. WAIT will be driven while the device is enabled and its state should be ignored. Page mode is enabled by
setting RCR[7] to HIGH. ADV# must be driven LOW during all page mode READ accesses. Due to refresh considerations, CE# must not
be LOW longer than tCEM.
Figure 5: Page Mode READ Operation (ADV# LOW)
CE#
tCEM
OE#
WE#
Address
DATA
LB#/UB#
Add0 Add1 Add2 Add3
tAA tAPA tAPA tAPA
D0 D1 D2 D3
Don’t Care
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EMC646SP16J.PDF ] | |
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