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EMC646SP16J PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 EMC646SP16J
기능 4Mx16 bit CellularRAM
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EMC646SP16J 데이터시트, 핀배열, 회로
Document Title
4Mx16 bit CellularRAM
Revision History
www.DataRSehveiest4ioUn.cNomo. History
0.0 Initial Draft
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Draft Date
July 05,2007
Remark
Preliminary
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : 690-717
Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to
your questions about device. If you have any questions, please contact the EMLSI office.
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EMC646SP16J pdf, 반도체, 판매, 대치품
Preliminary
EMC646SP16J
4Mx16 CellularRAM
List of Figures
Figure 1: Functional Block Diagram - 4 meg x 16 ................................................................................................................. 6
Figure 2: Power-Up Initialization Timing ............................................................................................................................... 9
Figure 3: READ Operation (ADV# LOW) .............................................................................................................................. 10
Figure 4: WRITE Operation (ADV# LOW) ............................................................................................................................. 11
Figure 5: Page Mode READ Operation (ADV# LOW) ........................................................................................................... 11
Figure 6: Burst Mode READ (4-word burst)........................................................................................................................... 12
Figure 7: Burst Mode WRITE (4-word burst).......................................................................................................................... 13
Figure 8: Refresh Collision During Variable-Latency READ Operation ................................................................................. 14
www.DatFaiSghuereet49U: .comWired or WAIT Configuration ................................................................................................................................. 15
Figure 10: Configuration Register WRITE, Asynchronous Mode, Followed by READ ARRAY Operation .............................. 17
Figure 11: Configuration Register WRITE, Synchronous Mode, Followed by READ ARRAY Operation ................................ 18
Figure 12: Register READ, Asynchronous Mode, Followed by READ ARRAY Operation ...................................................... 19
Figure 13: Register READ, Synchronous Mode, Followed by READ ARRAY Operation ........................................................ 20
Figure 14: Load Configuration Register .................................................................................................................................. 21
Figure 15: Read Configuration Register ................................................................................................................................. 21
Figure 16: Bus Configuration Register Definition .................................................................................................................... 22
Figure 17: WAIT Configuration During Burst Operation .......................................................................................................... 24
Figure 18: Latency Counter (Variable Initial Latency, No Refresh Collision) ........................................................................... 25
Figure 19: Latency Counter (Fixed Latency) ........................................................................................................................... 26
Figure 20: Refresh Configuration Register Mapping ............................................................................................................... 27
Figure 21: AC Input/Output Reference Waveform .................................................................................................................. 30
Figure 22: AC Output Load Circuit .......................................................................................................................................... 30
Figure 23: Initialization Period ................................................................................................................................................. 35
Figure 24: DPD Entry and Exit Timing Parameters ................................................................................................................. 35
Figure 25: Asynchronous READ ............................................................................................................................................. 36
Figure 26: Asynchronous READ Using ADV# ......................................................................................................................... 37
Figure 27: PAGE MODE READ .............................................................................................................................................. 38
Figure 28: Single-Access Burst READ Operation - Variable Latency ...................................................................................... 39
Figure 29: 4-Word Burst READ Operation - Variable Latency ................................................................................................. 40
Figure 30: Single-Access Burst READ Operation - Fixed Latency .......................................................................................... 41
Figure 31: 4-Word Burst READ Operation - Fixed Latency ..................................................................................................... 42
Figure 32: READ Burst Suspend ............................................................................................................................................ 43
Figure 33: Burst READ at End-of-Row (Wrap off) ................................................................................................................... 44
Figure 34: CE# - Controlled Asychronous WRITE .................................................................................................................. 45
Figure 35: LB#/UB# - Controlled Asychronous WRITE ........................................................................................................... 46
Figure 36: WE# - Controlled Asychronous WRITE ................................................................................................................. 47
Figure 37: Asynchronous WRITE Using ADV# ....................................................................................................................... 48
Figure 38: Burst WRITE Operation - Variable Latency Mode .................................................................................................. 49
Figure 39: Burst WRITE Operation - Fixed Latency Mode ...................................................................................................... 50
Figure 40: Burst WRITE at End-of-Row (Wrap off) ................................................................................................................. 51
Figure 41: Burst WRITE Followed by Burst READ .................................................................................................................. 52
Figure 42: Burst READ Interrupted by Burst READ or WRITE ................................................................................................ 53
Figure 43: Burst WRITE Interrupted by Burst WRITE or READ - Variable Latency Mode ....................................................... 54
Figure 44: Burst WRITE Interrupted by Burst WRITE or READ - Fixed Latency Mode ........................................................... 55
Figure 45: Asynchronous WRITE Followed by Burst READ ................................................................................................... 56
Figure 46: Asynchronous WRITE (ADV# LOW) Followed by Burst READ ............................................................................. 57
Figure 47: Burst READ Followed by Asynchronous WRITE (WE# - Controlled) ..................................................................... 58
Figure 48: Burst READ Followed by Asynchronous WRITE Using ADV# ............................................................................... 59
Figure 49: Asynchronous WRITE Followed by Asynchronous READ - ADV# LOW ............................................................... 60
Figure 50: Asynchronous WRITE Followed by Asynchronous READ ..................................................................................... 61
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EMC646SP16J 전자부품, 판매, 대치품
Preliminary
EMC646SP16J
4Mx16 CellularRAM
Table 1 : PIN Descriptions
Symbol
Type
Descriptions
A[21:0]
Input
Address inputs: Inputs for addresses during READ and WRITE operations. Addresses are internally latched
during READ and WRITE cycles. The address lines are also used to define the value to be loaded into the
BCR or the RCR.
CLK
(Note1)
Input
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Clock: Synchronizes the memory to the system operating frequency during synchronous operations. When
configured for synchronous operation, the address is latched on the first rising CLK edge when ADV# is
active. CLK is static LOW during asynchronous access READ and WRITE operations and during PAGE
READ ACCESS operations.
ADV#
(Note1)
Input
Address valid: Indiates that a valid address is present on the address inputs. Addresses can be latched on
the rising edge of ADV# during asynchronous READ and WRITE operations. ADV# can be held LOW during
asynchronous READ and WRITE operations.
CRE
Input
Control register enable: When CRE is HIGH, WRITE operations load the RCR or BCR, and READ operations
access the RCR, BCR, or DIDR.
CE#
Input
Chip enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into
standby or deep power-down mode.
OE#
Input Output enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled.
WE#
Input
Write enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a WRITE to either a
configuration register or to the memory array.
LB# Input Lower byte enable. DQ[7:0]
UB# Input Upper byte enable. DQ[15:8]
DQ[15:0] Input/Output Data inputs/outputs.
WAIT
(Note1)
Output
Wait: Provides data-valid feedback during burst READ and WRITE operations. The signal is gated by CE#.
WAIT is used to arbitrate collisions between refresh and READ/WRITE operations. WAIT is also asserted at
the end of a row unless wrapping within the burst length. WAIT is asserted and should be ignored during
asynchronous and page mode operations. WAIT is High-Z when CE# is HIGH.
RFU
- Reserved for future use.
Vcc Supply Device power supply: (1.70V.1.95V) Power supply for device core operation.
VccQ
Supply I/O power supply: (1.70V.1.95V) Power supply for input/output buffers.
Vss Supply Vss must be connected to ground.
VssQ
Supply VssQ must be connected to ground.
Note:
1. When using asynchronous mode or page mode exclusively, CLK and ADV# inputs can be tied to Vss. WAIT will be asserted but should be ignored during asynchronous
and page mode operations.
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