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EMC646SP16K PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 EMC646SP16K
기능 4Mx16 bit CellularRAM
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EMC646SP16K 데이터시트, 핀배열, 회로
Document Title
4Mx16 bit CellularRAM AD-MUX
Revision History
www.DataRSheeveits4iUo.cnomNo. History
0.0 Initial Draft
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Draft Date
July 13,2007
Remark
Preliminary
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : 690-717
Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
1
The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to
your questions about device. If you have any questions, please contact the EMLSI office.




EMC646SP16K pdf, 반도체, 판매, 대치품
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
List of Figures
Figure 1: Functional Block Diagram - 4 Meg x 16 ............................................................................................................................. 6
Figure 2: Power-Up Initialization Timing ........................................................................................................................................... 9
Figure 3: READ Operation ................................................................................................................................................................ 11
Figure 4: WRITE Operation .............................................................................................................................................................. 11
Figure 5: Burst Mode READ(4-word burst)........................................................................................................................................ 12
Figure 6: Burst Mode WRITE (4-word burst)...................................................................................................................................... 13
Figure 7: Refresh Collision During Variable-Latency READ Operation ............................................................................................. 14
Figure 8: Wired-OR WAIT Configuration ........................................................................................................................................... 15
www.DatFaiSghuereet49U: .coCmonfiguration Register WRITE, Asynchronous Mode, Followed by READ ARRAY Operation .......................................... 17
Figure 10: Configuration Register WRITE, Synchronous Mode, Followed by READ ARRAY Operation ............................................ 18
Figure 11: Register READ, Asynchronous Mode, Followed by READ ARRAY Operation .................................................................. 19
Figure 12: Register READ, Synchronous Mode, Followed by READ ARRAY Operation .................................................................... 20
Figure 13: Load Configuration Register .............................................................................................................................................. 22
Figure 14: Read Configuration Register ............................................................................................................................................. 22
Figure 15: Bus Configuration Register Definition ................................................................................................................................ 23
Figure 16: WAIT Configuration During Burst Operation ...................................................................................................................... 26
Figure 17: Latency Counter (Variable Initial Latency, No Refresh Collision) ....................................................................................... 27
Figure 18: Latency Counter (Fixed Latency) ....................................................................................................................................... 27
Figure 19: Refresh Configuration Register Mapping ........................................................................................................................... 28
Figure 20: AC Input / Output Reference Waveform ............................................................................................................................ 31
Figure 21: AC Output Load Circuit ...................................................................................................................................................... 31
Figure 22: Initialization Period ............................................................................................................................................................ 36
Figure 23: Asynchronous READ ......................................................................................................................................................... 36
Figure 24: Single-Access Burst READ Operation - Variable Latency ................................................................................................. 37
Figure 25: 4-Word Burst READ Operation - Variable Latency ............................................................................................................. 38
Figure 26: Single-Access Burst READ Operation - Fixed Latency ...................................................................................................... 39
Figure 27: 4-Word Burst READ Operation - Fixed Latency ................................................................................................................. 40
Figure 28: Burst READ Terminate at End-of-Row (Wrap off) .............................................................................................................. 41
Figure 29: Burst READ Row Boundary Crossing ................................................................................................................................ 42
Figure 30: Asynchronous WRITE ....................................................................................................................................................... 43
Figure 31: Burst WRITE Operation - Variable Latency Mode ............................................................................................................. 44
Figure 32: Burst WRITE Operation - Fixed Latency Mode .................................................................................................................. 45
Figure 33: Burst WRITE Terminate at End-of-Row (Wrap off) ............................................................................................................ 46
Figure 34: Burst WRITE Row Boundary Crossing .............................................................................................................................. 47
Figure 35: Burst WRITE Followed by Burst READ .............................................................................................................................. 48
Figure 36: Asynchronous WRITE Followed by Burst READ ............................................................................................................... 49
Figure 37: Burst READ Followed by Asynchronous WRITE ............................................................................................................... 50
Figure 38: Asynchronous WRITE Followed by Asynchronous READ ................................................................................................. 51
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EMC646SP16K 전자부품, 판매, 대치품
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Table 1: SIGNAL DESCRIPTIONS
Symbol
Type
Descriptions
A[21:16]
Input
Address inputs: Inputs for addresses during READ and WRITE operations. Addresses are internally latched
during READ and WRITE cycles. The address lines are also used to define the value to be loaded into the
BCR or the RCR.
CLK
www.DataS(hneoette41U).com
Input
Clock: Synchronizes the memory to the system operating frequency during synchronous operations. When
configured for synchronous operation, the address is latched on the first rising CLK edge when ADV# is
active. CLK must be static (HIGH or LOW) during asynchronous access READ and WRITE operations
when burst mode is enabled.
ADV#
(note1)
Input
Address valid: Indiates that a valid address is present on the address inputs. Addresses are latched on the
rising edge of ADV# during asynchronous READ and WRITE operations.
CRE
Input
Control register enable: When CRE is HIGH, WRITE operations load the RCR or BCR, and READ
operations access the RCR, BCR, or DIDR.
CE#
Input
Chip enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into
standby mode.
OE#
Input Output enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled.
WE#
Input
Write enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a WRITE to either a
configuration register or to the memory array.
LB# Input Lower byte enable. DQ[7:0]
UB# Input Upper byte enable. DQ[15:8]
Address/data I/Os: These pins are a multiplexed address/data bus. As inputs for address, these pins
A/DQ[15:0] Input/Output behave as A[15:0]. A[0] is the LSB of the 16-bit word address within the CellularRAM device. Address,
RCR, and BCR values are loaded with ADV# LOW. Data is input or output when ADV# is HIGH.
WAIT
(note1)
Output
Wait: Provides data-valid feedback during burst READ and WRITE operations. WAIT is used to arbitrate
collisions between refresh and READ/WRITE operations. WAIT is also asserted at the end of row unless
wrapping within the burst length. Wait should be ignored during asynchronous operations. WAIT is High-Z
when CE# is HIGH.
RFU
- Reserved for future use.
VCC
Supply Device power supply: (1.70V.1.95V) Power supply for device core operation.
VCCQ
Supply I/O power supply: (1.70V.1.95V) Power supply for input/output buffers.
VSS
Supply VSS must be connected to ground.
VSSQ
Supply VSSQ must be connected to ground.
Note:
1. When using asynchronous mode exclusively, CLK can be tied to VSSQ or VCCQ. WAIT should be ignored during asynchronous mode operations.
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