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PDF AN1515 Data sheet ( Hoja de datos )
| Número de pieza | AN1515 | |
| Descripción | Digital Output Angular Accelerometer | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AN1515 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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AN1515
APPLICATION NOTE
LIS1R02 (L6671):
A DIGITAL OUTPUT ANGULAR ACCELEROMETER
by F. Pasolini
1 INTRODUCTION
www.DataSheet4UT.choem LIS1R02 is a complete rotational accelerometer system based on a capacitive sensor that uses MEMS
technology, and a set of accompanying electronics that produces a digital output. The device is interfaced to
external hardware using a standard 3-wire serial interface that allows internal registers to be written and rota-
tional acceleration samples to be read.
The MEMS structure consists of a rotor and stator assembly in which capacitive variations occur when the rel-
ative position of the rotor with respect to the stator changes. These capacitive variations are on the order of 50
x 10-18 farads. The MEMS structure also includes actuation electrodes that allow the rotor position to be driven
externally by the processing electronics.
The electronic processing circuitry processes the capacitive variations that occur between the MEMS rotor and
stator. A SigmaDelta architecture is implemented that works to continually restore the rotor to nominal position.
The control effort, or the signal that drives the rotor to nominal, represents the rotational acceleration that is
present at the system location. This control effort is a binary bit stream that is decimated by the electronics to
provide a noise-reduced output
Gain and offset adjustments are applied to the decimated bit stream to produce the acceleration samples. Ac-
celerometer samples then are clocked into a four-deep data FIFO within the IC. The decimation and FIFO stag-
es are clocked in a free-running manner based on the selection of either an internal or external clock source.
1.1 Choosing an External Clock Source
Designers who will use the LIS1R02 to select the clock source which can be either from the CLK_IN pin, from
the internal oscillator or generated by using an embedded PLL.
When the CLK pin is selected as clock source, the designer has the ability to control the rate at which rotational
acceleration samples are generated within the LIS1R02. It takes exactly 224 CLK_IN cycles to generate one
new rotational acceleration sample, therefore the formula for determining the optimal frequency of the CLK_IN
signal is as follows:
Fout
=
-F---C----L---K----I--N--
224
(Eq. 2.1)
where FCLKIN is the frequency of the clock signal that is applied to the CLK_IN pin and Fout si the frequency
at which samples are produced.
If it is possible for the designer to implement a CLK_IN signal that satisfies equation 2.1 perfectly, then the de-
vice will generate one new acceleration sample at the desired rate (1/Ts). In practice, most designers will find it
difficult to supply a clock whose frequency satisfies equation 2.1. Generally, the designer will be restricted to
using a signal for CLK_IN that only approximates equation 2.1. In this case, the acceleration samples will be
generated at a rate that differs from the desired sample rate. The inclusion of the on-chip FIFO data buffer allows
for the proper handling of the accelerometer samples that are produced by the device.
In the case where:
FCLKIN
<
2----2---4--
Ts
(Eq. 2.2)
February 2002
1/12
1 page  
AN1515 APPLICATION NOTE
1.3 Registers: array organization
The internal registers are organized as follows:
Table 1. Registers Array
Address
Reg. Bank 1
Reg. Bank 2
0000
FIFO_Low
FIFO_Low
0001
not used
not used
0010
www.DataSheet4U.com
0011
FIFO_High
not used
FIFO_High
not used
0100
CTRL_Reg1
CTRL_Reg1
0101
CTRL_Reg2
CTRL_Reg2
0110
PLL_PRESC_MULT
FLASH_Reg_1
0111
PLL_MULT
FLASH_Reg_2
1000
IIR_A0 (*)
GAIN_Low (*)
1001
IIR_A1 (*)
GAIN_High (*)
1010
IIR_A2 (*)
OFFSET_Low (*)
1011
IIR_B1 (*)
OFFSET_High (*)
1100
IIR_B2 (*)
CURR_BANDGAP (*)
1101
IIR_SIGN_BIT (*)
BAND_CSACT_REG (*)
1110
DSC_Reg
CS_TRIM (*)
1111
MISC_Reg
MISC_Reg
Notes: (*) Value stored inside the embedded FLASH and loaded at boo
Reg. Bank 3
FIFO_Low
not used
FIFO_High
not used
CTRL_Reg1
CTRL_Reg2
PLL_COMPARE_REG
PLL_RST_VALUE_REG
not used
not used
not used
not used
not used
not used
not used
MISC_Reg
Due to the limited number of address bit (4) allowed by the SPI protocol and the high number of registers present
internally to the device, the registers have been spit and grouped into three banks.
To switch between Reg. Bank 1, Reg. Bank 2 and Reg. Bank 3 it is necessary to access the miscellaneous reg.
located @ address 1111.
The registers not loaded at boot can be written also before the boot procedure is completed.
No reading is allowed until the boot is done. The boot procedure takes 1800 clock pulses to be completed.
More information are reported in the paragraphs below.
5/12
5 Page 
AN1515 APPLICATION NOTE
1.4.16OFFSET_MSB (1011 -Reg. Bank 2-)
OH7 OH6 OH5 OH4 OH3 OH2 OH1 OH0
OH7-OH0
8 MSB of the digital offset correction value
1.5 Device initialization
Before using the device, the user must disable the Delayed Synchronous Conversion Option (bit DSC of
www.DataSheet4UC.cTomRL_REG2) and set the Sinc Order (bit SO of CTRL_REG2) to 2.
This is achieved by writing 0010 0010 inside the CTRL_REG2 register.
1.6 Circuit Board and Layout Considerations
In order to avoid, in the analog section, any kind of disturbances coming from the digital section, the 5V supply
and the ground are split between analog lines and digital lines. For this reason the VDD_DIGITAL 5V supply
and the GND_DIGITAL ground have been added. The two 5V supply lines must be powered up and down si-
multaneously (a maximum 0.3V difference between them is allowed. The two 5V supply lines and the two
ground lines could be derived from a single low-voltage supply and a single ground but must be connected to
the chip using two separate decoupling capacitors.
The LIS1R02 IC by default expects a master clock coming into the CLK_IN pin. This master clock frequency
must be lower than 6MHz. A ground plane must be located under the chip to help prevent any disturbance to
the LIS1R02 sensor.
Each of the two power supplies requires decoupling capacitors. It is recommended that each VDD pin (analog
and digital) have a 0.22µF as near as possible to the chip pin. A 22µF electrolytic capacitor on the supply line
is also advised. As close as possible to the REF_CAP pin (pin 8), two decoupling capacitors must be placed. A
0.22µF electrolytic and a 220pF ceramic or polyester are strongly recommended.
Due to the high sensitivity of this device maximum care must be taken during board layout to avoid any kind of
coupling between CLK_IN, power supplies and grounds tracks. In order to avoid any performance loss, the
REF_CAP pin and the board trace that connects it must be far from any kind of noisy signal (i.e. CLK_IN).
11/12
11 Page | ||
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| PDF Descargar | [ Datasheet AN1515.PDF ] | |
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