|
|
PDF MT8986 Data sheet ( Hoja de datos )
| Número de pieza | MT8986 | |
| Descripción | Multiple Rate Digital Switch | |
| Fabricantes | Mitel Networks Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MT8986 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
CMOS ST-BUS™ FAMILY MT8986
®
Multiple Rate Digital Switch
Features
• 256 x 256 or 512 x 256 switching configurations
• 8-bit or 4-bit channel switching capability
• Guarantees frame integrity for wideband
channels
• Automatic identification of ST-BUS/GCI
www.DataSheet4U.com interfaces
• Accepts serial streams with data rates up to
8.192 Mb/s
• Rate conversion from 2.048 Mb/s to 4.096 or
8.192 Mb/s and vice-versa
• Programmable frame offset on inputs
• Per-channel three-state control
• Per-channel message mode
• Control interface compatible to Intel/Motorola
CPUs
• Low power consumption
Applications
• Medium size digital switch matrices
• Hyperchannel switching (e.g., ISDN H0)
• MVIP™ interface functions
• Serial bus control and monitoring
• Centralized voice processing systems
• Voice/Data multiplexer
• 32 kbit/s channel switching
ISSUE 3
May 1995
Ordering Information
MT8986AC 40 Pin Ceramic DIP
MT8986AE 40 Pin Plastic DIP
MT8986AP 44 Pin PLCC
MT8986AL 44 Pin QFP
-40°C to +85°C
Description
The Multiple Rate Digital Switch (MRDX) is an
upgraded version of MITEL's MT8980D Digital
Switch (DX). It is pin compatible with the MT8980D
and retains all of its functionality. This device is
designed to provide simultaneous connections (non-
blocking) for up to 256 64kb/s channels or blocking
connections for up to 512 64kb/s channels. The
serial inputs and outputs connected to MT8986 may
have 32 to 128 64kb/s channels per frame with data
rates ranging from 2048 up to 8192 kb/s. The
MT8986 provides per-channel selection between
variable and constant throughput delays allowing
voice and grouped data channels to be switched
without corrupting the data sequence integrity.
In addition, the MT8986 can be used for switching of
32 kb/s channels in ADPCM applications. The
MT8986 is ideal for medium size mixed voice and
data switching/processing applications.
VDD VSS
ODE
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
STi8
STi9
* STi10
* STi11
* STi12
* STi13
* STi14
* STi15
Serial
to
Parallel
Converter
Timing
Unit
Multiple Buffer Data
Memory
Internal Registers
Microprocessor
Interface
Output
MUX
Connection
Memory
Parallel
to
Serial
Converter
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
STo8 *
STo9 *
* 44 Pin only
CLK FR AS/ IM DS CS R/W A0/ DTA AD7/
ALE * RD
WR A7
AD0
CSTo
Figure 1 - Functional Block Diagram
2-63
1 page  
MT8986
DEVICE OVERVIEW
With the integration of voice, video and data services
in the same network, there has been an increasing
demand for systems which ensure that data at N x
64 kbit/s rates maintain sequence integrity while
being transported through time-slot interchange
circuits. This requirement demands time-slot
interchange devices which perform switching with
constant throughput delay for wideband data
applications while guaranteeing minimum delay for
voice channels.
The MT8986 device meets the above requirement
www.DataSheet4U.caonmd allows existing systems based on the MT8980D
to be easily upgraded to maintain the data integrity
when wideband data is transported. The device is
designed to switch 32, 64 or N x 64 kbit/s data. The
MT8986 can provide frame integrity for data
applications and minimum throughput switching
delay for voice applications on a per channel basis.
The serial streams of the MT8986 device can
operate at 2.048, 4.096 or 8.192 Mbit/s and are
arranged in 125 µs wide frames which contain 32, 64
and 128 channels, respectively. In addition, a built-in
rate conversion circuit allows the user to
interconnect various backplane speeds like 2.048 or
4.096 or 8.192 Mb/s while maintaining the control of
throughput delay function on a per-channel basis.
By using Mitel Message mode capability, the
microprocessor can access input and output time-
slots on a per channel basis to control external
circuits or other ST-BUS devices. The MT8986
automatically identifies the polarity of the frame
synchronization input signal and configures its serial
port to be compatible to both ST-BUS and GCI
formats.
In the 44 pin packages, two different microprocessor
bus interfaces can be selected through an input
mode pin (IM): Non-Multiplexed or Multiplexed.
These interfaces provide compatibility with Intel/
National multiplexed and Motorola Multiplexed/Non-
Multiplexed buses. In 44 pin, the MT8986 provides a
16 x 8 switching configuration to form a 512 x 256
channel blocking matrix. Also, a flexible Stream Pair
Selection operation allows the software selection of
which pair of input and output streams can be
connected to an internal 128 x 128 matrix. See
Switching Configurations section for details.
Functional Description
A functional Block Diagram of the MT8986 device is
shown in Figure 1. Depending on the application, the
MT8986 device receives TDM serial data at different
rates and from different number of serial streams.
Data and Connect Memories
For all data rates, the received serial data is
converted to parallel format by the serial to parallel
converters and stored sequentially in a Data
Memory. Depending on the selected operation
programmed in the IMS (Interface Mode Select)
register, the Data Memory may have up to 512 bytes
in use. The sequential addressing of the Data
Memory is performed by an internal counter which is
reset by the input 8 kHz frame pulse (FR) marking
the frame boundaries of the incoming serial data
streams.
Data to be output on the serial streams may come
from two sources: Data Memory or Connect Memory.
Locations in the Connect Memory, which is split into
HIGH and LOW parts, are associated with particular
ST-BUS output streams. When a channel is due to
be transmitted on an ST-BUS output, the data for the
channel can either be switched from an ST-BUS
input as in connection mode or it can be from the
Connect Memory Low as in message mode. Data
destined for a particular channel on the serial output
stream is read from the Data Memory or Connect
Memory Low during the previous channel time-slot.
This allows enough time for memory access and
parallel to serial conversion.
Connection and Message Modes
In connection mode, the addresses of the input
source data for all output channels are stored in the
Connect memories High (CMH) and Low (CML). The
CML and CMH are mapped so that each location
corresponds to an output channel on the output
streams. The number of source address bits in CMH
and CML to be utilized varies according to the
switching configuration selected in the IMS register.
For details on the use of the source address data
(CAB and SAB bits), see CMH and CML bit descrip-
tion (Figures 5 & 6). Once the source address bits
are programmed by the CPU, the contents of the
Data Memory at the selected address are transferred
to the parallel-to-serial converters. By having the
output channel specify the source channel through
the connect memory, the user can route the same
input channel to several output channels, allowing
broadcast facility within the switch.
In message mode the CPU writes data to the
Connect Memory Low locations corresponding to the
output link and channel number. The contents of the
Connect Memory Low are transferred directly to the
parallel-to-serial converter one channel before it is to
2-67
5 Page 
MT8986
The Control and Interface Mode Selection registers
together control all the major functions of the device.
The Interface Mode Select register should be set up
during system power-up to establish the desired
switching configuration as explained in the Serial
Interface and Switching Configurations sections.
The Control register is dynamically used by the CPU
to control switching operations in the MT8986. The
Control register selects the device's internal
memories and its subsections to specify the input
and output channels selected for switching
procedures.
www.DataSheet4U.cTohme data in the Control register consists of Split
memory and Message mode bits, Memory select and
Stream Address bits. The memory select bits allow
the Connect Memory HIGH or LOW or the Data
Memory to be chosen, and the Stream Address bits
define an internal memory subsections
corresponding to input or output ST-BUS streams.
Bit 7 (Slip Memory) of the Control register allows split
memory operation whereby reads are from the Data
memory and writes are to the Connect Memory
LOW.
The Message Enable bit (bit 6) places every output
channel on every output stream in message mode;
i.e., the contents of the Connect Memory LOW
(CML) are output on the ST-BUS output streams
once every frame unless the ODE input pin is LOW.
If ME bit is HIGH, then the MT8986 behaves as if bits
2 (Message Channel) and 0 (Output Enable) of every
Connect Memory HIGH (CMH) locations were set to
HIGH, regardless of the actual value. If ME bit is
LOW, then bit 2 and 0 of each Connect Memory
HIGH location function normally. In this case, if bit 2
of the CMH is HIGH, the associated ST-BUS output
channel is in Message mode. If bit 2 of the CMH is
LOW, then the contents of the SAB and CAB bits of
the CMH and CML define the source information
(stream and channel) of the time-slot that is to be
switched to an output.
If the ODE input pin is LOW, then all serial outputs
are high-impedance. If ODE is HIGH, then bit 0
(Output Enable) of the CMH location enables (if
HIGH) or disables (if LOW) the output drivers for the
corresponding individual ST-BUS output stream and
channel.
The contents of bit 1 (CSTo) of each Connection
Memory High location is output on CSTo pin once
every frame. The CSTo pin is a 2048 Mbit/s output
which carries 256 bits. If CSTo bit is set HIGH, the
corresponding bit on CSTo output is transmitted
HIGH. If CSTo bit is LOW, the corresponding bit on
the CSTo output is transmitted LOW. The contents of
the 256 CSTo bits of the CMH are transmitted
sequentially on to the CSTo output pin and are
synchronous to the 2.048 Mb/s ST-BUS streams. To
allow for delay in any external control circuitry the
contents of the CSTo bit is output one channel before
the corresponding channel on the ST-BUS streams.
For example, the contents of CSTo bit in position 0
(ST0, CH0) of the CMH, is transmitted
synchronously with ST-BUS channel 31, bit 7. The
contents of CSTo bit in position 32 (ST1, CH0) of the
A7 A6 A5 A4 A3 A2 A1 A0
Location
XX0 0 0 0 0 0
Control Register
XX0 0 0 0 0 1
Interface Mode Select Register
XX0 0 0 0 1 0
Stream Pair Select Register
XX0 0 0 0 1 1
Frame Input Offset Register
00100000
Channel 0*
00100001
• •1• • • ••
• •1• • • ••
00111111
Channel 1*
•
•
Channel 31*
01100000
Channel 32**
01100001
• •1• • • ••
• •1• • • ••
01111111
Channel 33**
•
•
Channel 63**
10100000
• •1• • • ••
• •1• • • ••
11111111
Channel 64***
•
•
Channel 127***
Table 5. Address Memory Map
*: channels 0 to 31 are used in 2.048 Mb/s (8 x 8, 16 x 8 and 10 x 10)
**: channels 0 to 63 are used in 4.096 Mb/s (Nibble Switching, 4 x 4, 8 x 4 or Different I/O rates)
***: channels 0 to 127 are used in 8.192 Mb/s (2 x 2 or Different I/O rates)
2-73
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MT8986.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MT8980D | ISO-CMOS ST-BUS FAMILY Digital Switch |  Mitel Networks |
| MT8980D | Digital Switch |  Zarlink |
| MT8981D | Digital Switch | Mitel Networks Corporation |
| MT8981D | ISO-CMOS ST-BUS |  Zarlink Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |