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PDF P4C163L Data sheet ( Hoja de datos )
| Número de pieza | P4C163L | |
| Descripción | ULTRA HIGH SPEED 8K x 9 STATIC CMOS RAMS | |
| Fabricantes | Pyramid Semiconductor Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de P4C163L (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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P4C163/P4C163L
ULTRA HIGH SPEED 8K x 9
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 25/35ns (Commercial)
– 25/35/45ns (Military)
Low Power Operation (Commercial/Military)
www.DataSheet4UO.coumtput Enable and Dual Chip Enable Control
Functions
Single 5V±10% Power Supply
Data Retention with 2.0V Supply, 10 µA Typical
Current (P4C163L Military)
Common I/O
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil DIP, SOJ
– 28-Pin 350 x 550 mil LCC
– 28-Pin CERPACK
DESCRIPTION
The P4C163 and P4C163L are 73,728-bit ultra high-speed
static RAMs organized as 8K x 9. The CMOS memories re-
quire no clocks or refreshing and have equal access and
cycle times. Inputs are fully TTL-compatible. The RAMs
operate from a single 5V±10% tolerance power supply.
With battery backup, data integrity is maintained for supply
voltages down to 2.0V. Current drain is 10 µA from a 2.0V
supply.
Access times as fast as 25 nanoseconds are available, per-
mitting greatly enhanced system operating speeds. CMOS
is used to reduce power consumption in both active and
standby modes.
The P4C163 and P4C163L are available in 28-pin 300 mil
DIP and SOJ, 28-pin 350 x 550 mil LCC, and 28-pin
CERPACK packages providing excellent board level densi-
ties.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (P5, C5), SOJ (J5)
CERPACK (F4) SIMILAR
LCC (L5)
Document # SRAM120 REV C
Revised August 2006
1
1 page  
READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
READ CYCLE NO. 3 (CE1, CE2 CONTROLLED)(5,7,10)
www.DataSheet4U.com
P4C163/163L
Notes:
9. READ Cycle Time is measured from the last valid address to the first
transitioning address.
10. Transitions caused by a chip enable control have similar delays
irrespective of whether CE1 or CE2 causes them.
Document # SRAM120 REV C
Page 5 of 12
5 Page 
Pkg #
# Pins
Symbol
A
A1
b
b2
C
D
E1
E
e
eB
L
www.DataSheet4U.coαm
P5
28 (300 mil)
Min Max
- 0.210
-
0.014 0.023
0.045 0.070
0.008 0.014
1.345 1.400
0.270 0.300
0.300 0.380
0.100 BSC
- 0.430
0.115 0.150
0° 15°
PLASTIC DUAL IN-LINE PACKAGE
P4C163/163L
Document # SRAM120 REV C
Page 11 of 12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet P4C163L.PDF ] | |
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