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PDF P4C165 Data sheet ( Hoja de datos )
| Número de pieza | P4C165 | |
| Descripción | ULTRA HIGH SPEED 8K x 8 RESETTABLE STATIC CMOS RAM | |
| Fabricantes | Pyramid Semiconductor Corporation | |
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P4C165
ULTRA HIGH SPEED 8K x 8
RESETTABLE STATIC CMOS RAM
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 15/20/25 ns (Commercial)
– 20/25/35 (Industrial)
www.DataSheet4UL.coomw Power Operation
Chip Clear Function
Output Enable and Dual Chip Enable Control
Functions
Single 5V±10% Power Supply
Common Data I/O
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 28-Pin Plastic DIP (300 mil)
DESCRIPTION
The P4C165 is a 65,536-bit ultra high-speed static RAM
organized as 8K x 8. The RAM features a reset control to
enable clearing all words to zero within two cycle times.
The CMOS memory requires no clocks or refreshing and
has equal access and cycle times. Inputs are fully TTL-
compatible. The RAM operates from a single 5V±10%
tolerance power supply.
Access times as fast as 15 nanoseconds are available,
permitting greatly enhanced system operating speeds.
In full standby mode with CMOS inputs, power consump-
tion is only 5.5 mW for the P4C165.
The P4C165 is available in a 28-pin 300 mil DIP.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
15D19BIP (P5)
Document # SRAM117 Rev OR
Revised October 2005
1
1 page  
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym. Parameter
tWC Write Cycle Time
tCW Chip Enable Time to End of Write
tAW Address Valid to End of Write
tAS Address Set-up Time
tWP Write Pulse Width
tAH Address Hold Time
tDW Data Valid to End of Write
www.DataSheet4U.com
tDH
Date
Hold
Time
tWZ Write Enable to Output in High Z
tOW Output Active from End of Write
WRITE CYCLE NO. 1 (WE CONTROLLED)(11)
P4C165
-15 -20 -25 -35 Unit
Min Max Min Max Min Max Min Max
15 20 25 35 ns
12 15 18 25 ns
12 15 18 25 ns
0 0 0 0 ns
12 15 18 20 ns
0 0 0 0 ns
9 11 13 15 ns
0 0 0 0 ns
7 8 10 14 ns
3 3 3 3 ns
Notes:
11. CE1 and WE must be LOW, and CE2 HIGH for WRITE cycle.
12. OE is LOW for this WRITE cycle to show tWZ and tOW.
13. If CE1 goes HIGH, or CE2 goes LOW, simultaneously with WE HIGH,
the output remains in a high impedance state.
14. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Document # SRAM117 Rev OR
5
Page 5 of 9
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet P4C165.PDF ] | |
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