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PDF ICS9FG104 Data sheet ( Hoja de datos )
| Número de pieza | ICS9FG104 | |
| Descripción | Frequency Generator | |
| Fabricantes | Integrated Device Technology | |
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Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
DATASHEET
ICS9FG104
Description
The ICS9FG104 is a Frequency Timing Generator that provides 4
differential output pairs that are compliant to the Intel CK410
specification. It also provides support for PCI-Express and SATA.
The part synthesizes several output frequencies from either a
14.31818 Mhz crystal or a 25 MHz crystal. The device can also be
driven by a reference input clock instead of a crystal. It provides
outputs with cycle-to-cycle jitter of less than 50 ps and output-to-
output skew of less than 35 ps. The ICS9FG104 also provides a copy
of the reference clock. Frequency selection can be accomplished via
strap pins or SMBus control.
www.DaKtaeSyhSepete4cUif.cicoamtions
• Output cycle-to-cycle jitter < 50 ps
• Output to output skew < 35 ps
• +/-300 ppm frequency accuracy on output clocks
• +/- 150 ppm frequency accuracy @ 100 MHz outputs
• 28-pin SSOP/TSSOP package
• Available in RoHS compliant packaging
Features/Benefits
• Generates common frequencies from 14.318 MHz or
25 MHz
• Crystal or reference input
• 4 - 0.7V current-mode differential output pairs
• Supports Serial-ATA at 100 MHz
• Two spread spectrum modes: 0 to -0.5 downspread
and +/-0.25% centerspread
• Unused inputs may be disabled in either driven or Hi-Z
state for power management.
• M/N Programming
Funtional Block Diagram
XIN/CLKIN
X2
2
OSC
PROGRAMMABLE
SPREAD PLL
STOP
LOGIC
4
REFOUT
DIF(3:0)
SPREAD
SEL14M_25M#
DIF_STOP#
FS(2:0)
SDATA
SCLK
CONTROL
LOGIC
IREF
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1
ICS9FG104 REV K 04/12/07
1 page  
ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD)
Byte 0
Pin #
Name
Control Function
Type
0
1
Bit 7
17
FS31
RW
Bit 6
Bit 5
6
24
FS21
FS11
RW See Frequency Selection Table,
RW Page 1
Bit 4
25
FS01
RW
Bit 3
16
Spread Enable1
RW Off
On
Bit 2
-
Enable Software Control of Frequency, Spread Enable
(Spread Type always Software Control)
RW Hardware Select Software Select
PWD
Pin 17
Pin 6
Pin 24
Pin 25
Pin 16
0
Bit 1
Bit 0
DIF_STOP# drive mode
SPREAD TYPE
RW Driven
RW Down
Hi-Z
Center
0
0
Notes:
1. These bits reflect the state of the corresponding pins at power up, but may be written to
www.DaiftaBySteh0e,ebtit42Uis.csoetmto '1'. FS3 is the SEL14M_25M# pin.
SMBus Table: Output Enable Register
Byte 1
Pin #
Name
Bit 7
-
Bit 6
-
DIF_3 EN
Bit 5
-
DIF_2 EN
Bit 4
-
Bit 3
-
Bit 2
-
DIF_1 EN
Bit 1
-
DIF_0 EN
Bit 0
-
Control Function
Reserved
Output Enable
Output Enable
Reserved
Reserved
Output Enable
Output Enable
Reserved
Type
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
1
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
SMBus Table: Output Stop Control Register
Byte 2
Pin #
Name
Control Function
Bit 7
-
Reserved
Bit 6
-
DIF_3 STOP EN
Free Run/ Stop Enable
Bit 5
-
DIF_2 STOP EN
Free Run/ Stop Enable
Bit 4
-
Reserved
Bit 3
-
Reserved
Bit 2
-
DIF_1 STOP EN
Free Run/ Stop Enable
Bit 1
-
DIF_0 STOP EN
Free Run/ Stop Enable
Bit 0
-
Reserved
Type
RW
RW
RW
RW
0
Free-run
Free-run
Free-run
Free-run
1
Stop-able
Stop-able
Stop-able
Stop-able
PWD
0
0
0
0
0
0
0
0
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
5
ICS9FG104 REV K 04/12/07
5 Page 
ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, Ι REF = 475Ω
PARAMETER
SYMBOL
CONDITIONS
MIN
Output Impedance
Zo1
VO = Vx
3000
Voltage High
Voltage Low
VHigh
VLow
Statistical measurement on single
ended signal using oscilloscope
math function.
660
-150
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
Measurement on single ended
signal using absolute value.
-300
250
TYP MAX
850
150
1150
550
UNITS
Ω
mV
mV
mV
Crossing Voltage (var)
d-Vcross Crossing variation over all edges
140 mV
Long Accuracy
ppm
see Tperiod min-max values
-300
300 ppm
www.DataSheet4U.com
400MHz nominal
400MHz spread
2.4993
2.4993
2.5008
2.5133
ns
ns
333.33MHz nominal
2.9991
3.0009 ns
333.33MHz spread
2.9991
3.016
ns
266.66MHz nominal
3.7489
3.7511 ns
266.66MHz spread
3.7489
3.77 ns
Average period
Tperiod
200MHz nominal
200MHz spread
4.9985
4.9985
5.0015
5.0266
ns
ns
166.66MHz nominal
5.9982
6.0018 ns
166.66MHz spread
5.9982
6.0320 ns
133.33MHz nominal
7.4978
7.5023 ns
133.33MHz spread
7.4978
5.4000 ns
100.00MHz nominal
9.9970
10.0030 ns
100.00MHz spread
9.9970
10.0533 ns
400MHz nominal/spread
2.4143
ns
333.33MHz nominal/spread 2.9141
ns
Absolute min period
Tabsmin
266.66MHz nominal/spread
200MHz nominal/spread
166.66MHz nominal/spread
3.6639
4.8735
5.8732
ns
ns
ns
133.33MHz nominal/spread 7.3728
ns
100.00MHz nominal/spread 9.8720
ns
Rise Time
tr
VOL = 0.175V, VOH = 0.525V
175
700 ps
Fall Time
tf
VOH = 0.525V VOL = 0.175V
175
700 ps
Rise Time Variation
d-tr
125 ps
Fall Time Variation
Duty Cycle
Skew, output to output
Jitter, PCI-e SRC phase
d-tf
dt3
tsk3
tjPCI-ephase14
Measured Differentially
VT = 50%
22MHz/1.5MHz/1.5MHz/10ns,
14.31818 MHz REF Clock
45
125 ps
55 %
35 ps
42 ps
Jitter, PCI-e SRC phase
tjPCI-ephase25
22MHz/1.5MHz/1.5MHz/10ns,
25 MHz REF Clock
39 ps
Jitter, Cycle to cycle
tjcyc-cyc
Measured Differentially
50 ps
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
or 25 MHz
3 Figures are for down spread.
4 This figure is the peak-to-peak phase jitter as defined by PCI-SIG for a PCI Express reference clock. Please visit
http://www.pcisig.com for additional details
5 +/- 150 ppm for 100 MHz outputs
NOTES
1
1
1
1
1
1
1
1,2,5
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
1
1
1
1
4
4
4
1
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG104 REV K 04/12/07
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ICS9FG104.PDF ] | |
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