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T6B65AFG 데이터시트 PDF




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부품번호 T6B65AFG 기능
기능 COLUMN DRIVER LSI
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T6B65AFG 데이터시트, 핀배열, 회로
T6B65AFG
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
T6B65AFG
Column Driver LSI for Dot Matrix Graphic LCD’s
Manufactured using the CMOS process, the T6B65AFG is a
column (segment) driver for small-to-medium-sized dot matrix
graphic LCDs. Use of the T6B65AFG enables power dissipation to
be reduced. It is designed to connect directly to an 8-bit
microprocessor unit. The MPU can program all operating modes
for the T6B65AFG asynchronously.
www.DataSheet4U.com The T6B65AFG stores display data transferred from an MPU
in its internal display RAM. The contents of the internal display
RAM correspond to the image on the LCD screen and are used to
generate the LCD drive signal.
Three T6B65AFGs can be combined with a Toshiba T6B66BFG
row (common) driver to drive a 240-dot by 65-dot LCD screen.
The T6B65AFG is lead (Pb)-free product.
Features
QFP100-P-1420-0.65Q
Weight: 1.6 g (typ.)
Dot matrix graphic LCD column driver with display RAM
Display RAM capacity
: 64 lines × 10 pages × 8 bits = 5120 bits (display area)
1 line × 10 pages × 8 bits = 80 bits (flag area)
Total = 5200 bits
LCD drive outputs
: 80
Interface
: 80-family MPU (8-bit)
RAM data directly echoed to LCD
(1) RAM bit data = 1 …………… ON
(2) RAM bit data = 0 …………… OFF
Duty: Can be controlled by the T6B66BFG.
Display OFF functions
Various functions
X/Y-counter selection, Up/Down mode selection, X-address setting,
Y-address setting, Display Start Line setting, “Status Read”, display data read/write
Low power consumption
Logic power supply
: 2.7 to 5.5 V
CMOS Si-Gate process
100-pin-plastic flat package
1 2005-06-01




T6B65AFG pdf, 반도체, 판매, 대치품
Pin Functions
T6B65AFG
Pin Name
Pin No .
I/O
Function
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SEG1 to SEG80
CL
PM
/φ
DB0 to DB7
D/I
/ WR
/ CE
/ RST
VDD, VSS
VLC2, 3, 5
1 to 80
96
95
94
81 to 88
93
92
91
89
90, 97
98, 99, 100
Output
Input
Input
Input
I/O
Input
Input
Input
Input
Column driver outputs
Shift clock pulse
Pre-frame signal input
Clock signal
Data bus
Data/instruction select signal input
Write select signal input
Chip enable signal input
Reset signal input: / RST = L ......... Reset state
Power supply
Power supply for LCD drive
Note 1: D / I = H ……………… Indicates that the data on DB0 to DB7 is display data.
D / I = L ……………… Indicates that the data on DB0 to DB7 is control data.
Note 2: / WR = H ………..…… Read is selected.
/ WR = L ………..…… Write is selected.
Note 3: When writing………… Data on DB0 to DB7 is latched on the rising edge of / CE.
When reading…..…… Data appears at DB0 to DB7 while / CE is LOW.
(Note 1)
(Note 2)
(Note 3)
Function of Each Block
Interface
The T6B65AFG is equipped with interface logic enabling interfacing to an 8-bit (80-family) MPU.
Input register
This register holds 8-bit data from the MPU. Instruction and display data are distinguished by the D / I
signal and the 8-bit data.
Output register
This register holds 8-bit data from the display RAM. When display data is read, the display data in the
address is copied to this register. The address is then automatically incremented or decremented. When an
address is set, therefore, the correct data does not appear on the first data reading. The data at the specified
address appears on the second data reading.
X, Y (Page)-address counter
The X, Y (Page)-address counter holds a display RAM address. Reading or writing to the display RAM causes
the X / Y-address to increment or decrement automatically.
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T6B65AFG 전자부품, 판매, 대치품
Test mode select
T6B65AFG
Code
/ WR D / I DB7
000
················································
0001 * *
DB0
* *: INVALID
This command selects the Test mode. Do not use this command.
Set Z-address (Display Start Line)
Code
/ WR D / I DB7
000
················································
1AAAAA
DB0
A
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This command specifies which RAM line (0 to 63) is displayed at the top of the screen. When the display
duty is more than 1 / 64 (e.g., 1 / 33, 1 / 49), display begins at a line within the range 1 to 33 or 1 to 49.
This command only applied to display RAM. The line following the last line of the display RAM is the flag
RAM.
Set X-address
Code
/ WR D / I DB7
001
················································
0AAAAA
DB0
A
This command sets the X-address (0 to 63). When the Counter Up / Down Select command selects this
address counter, reading or writing to the RAM causes the X-address to increment or decrement
automatically.
In X-Counter / Up mode, if the previous X-address is 63, the new X-address after the increment will be 0
and the Y (page)-address will be incremented. In Y-Counter / Down mode, if the previous X-address is 0, the
new X-address after the decrement will be 63 and the Y (page)-address will be decremented.
Set Y (Page)-address
Code
/ WR D / I DB7
001
001
················································
1 * 1AAA
1 * 0AAA
DB0
A Flag mode
A Display RAM mode *: INVALID
This command sets the Y (page) -address and also selects Flag mode or Display RAM mode.
In Flag mode, you can read data from or write data to Flag RAM only but cannot access the Display RAM.
In Display RAM mode, you can read data from or write data to the Display RAM only but cannot access
the Flag RAM.
When the Counter Up / Down Select command selects this address counter, reading from or writing to the
RAM causes the Y-address to increment or decrement automatically.
In Y-Counter / Up mode, if the previous Y-address is 9, the new Y-address after the increment will be 0 and
the X-address will be incremented. In Y-Counter / Down mode, if the previous Y-address is 0, the new
Y-address after the decrement will be 9 and the X-address will be decremented.
In Flag mode, only Y-Counter / Up or Down mode is permitted.
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T6B65AFG

COLUMN DRIVER LSI

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