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부품번호 | TY30N50E 기능 |
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기능 | Power Field Effect Transistor | ||
제조업체 | Motorola Semiconductors | ||
로고 | |||
전체 8 페이지수
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Designer's
™ Data Sheet
TMOS E-FET .™
Power Field Effect Transistor
N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS power FET is designed to withstand high
energy in the avalanche and commutation modes. This new energy
efficient design also offers a drain–to–source diode with fast
recovery time. Designed for high voltage, high speed switching
applications in power supplies, converters, PWM motor controls,
and other inductive loads. The avalanche energy capability is
specified to eliminate the guesswork in designs where inductive
www.DataSheet4loUa.cdosmare switched and offer additional safety margin against
unexpected voltage transients.
• Avalanche Energy Specified
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
®
D
Order this document
by MTY30N50E/D
MTY30N50E
Motorola Preferred Device
TMOS POWER FET
30 AMPERES
500 VOLTS
RDS(on) = 0.15 OHM
G
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1 MΩ)
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
Drain Current — Continuous @ TC = 25°C
Drain Current — Single Pulse (tp ≤ 10 µs)
Total Power Dissipation
Derate above 25°C
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 30 Apk, L = 10 mH, RG = 25 Ω )
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
CASE 340G–02, STYLE 1
TO–264
S
Symbol
VDSS
VDGR
VGS
VGSM
ID
IDM
PD
TJ, Tstg
EAS
Value
500
500
± 20
± 40
30
80
300
2.38
– 55 to 150
3000
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
°C
mJ
RθJC
RθJA
TL
0.42 °C/W
40
260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc.
TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
©MMoottoororolal,aInTc.M19O9S5 Power MOSFET Transistor Device Data
1
MTY30N50E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
www.DataSheet4thUe.cpomlateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
24000
20000
VDS = 0 V
Ciss
16000
VGS = 0 V
TJ = 25°C
12000 Crss
8000
Ciss
4000 Coss
Crss
0
10 5 0 5 10 15 20 25
VGS VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7a. Capacitance Variation
100000
VGS = 0 V
10000
TJ = 25°C
Ciss
1000
Coss
100 Crss
10
10 100 1000
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7b. High Voltage Capacitance
Variation
4 Motorola TMOS Power MOSFET Transistor Device Data
4페이지 PACKAGE DIMENSIONS
–B–
N
R
–Y–
www.DataSheet4U.com
123
0.25 (0.010) M T B M
–Q–
U
A
L
P
K
–T–
C
E
F 2 PL
W
G
D 3 PL
0.25 (0.010) M Y Q S
J
H
CASE 340G–02
TO–264
ISSUE E
MTY30N50E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 2.8 2.9 1.102 1.142
B 19.3 20.3 0.760 0.800
C 4.7 5.3 0.185 0.209
D 0.93 1.48 0.037 0.058
E 1.9 2.1 0.075 0.083
F 2.2 2.4 0.087 0.102
G 5.45 BSC
0.215 BSC
H 2.6 3.0 0.102 0.118
J 0.43 0.78 0.017 0.031
K 17.6 18.8 0.693 0.740
L 11.0 11.4 0.433 0.449
N 3.95 4.75 0.156 0.187
P 2.2 2.6 0.087 0.102
Q 3.1 3.5 0.122 0.137
R 2.15 2.35 0.085 0.093
U 6.1 6.5 0.240 0.256
W 2.8 3.2 0.110 0.125
STYLE 1:
PIN 1.
2.
3.
GATE
DRAIN
SOURCE
Motorola TMOS Power MOSFET Transistor Device Data
7
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TY30N50E | Power Field Effect Transistor | Motorola Semiconductors |
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