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PDF SH69P42 Data sheet ( Hoja de datos )
| Número de pieza | SH69P42 | |
| Descripción | OTP 4-Bit Microcontroller | |
| Fabricantes | Sino Wealth Microelectronic | |
| Logotipo |  |
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SH69P42
OTP 4-bit Microcontroller with SAR 8-bit A/D Converter
www.DataSheeFt4eUa.ctoumres
SH6610D-based single-chip 4-bit microcontroller with
8-bit SAR A/D converter
OTP ROM: 3072 X 16 bits
RAM: 192 X 4 bits
System register: 48 X 4 bits
Data memory: 144 X 4 bits
Operation voltage:
fOSC = 400kHz - 4MHz, VDD = 2.4V - 5.5V
fOSC = 8MHz, VDD = 4.5V - 5.5V
16 CMOS bi-directional I/O pins
Built-in pull-up for I/O port
Two 8-bit auto re-load timer/counter, One can switch to
external clock source
8-level subroutine nesting (including interrupts)
Powerful interrupt sources:
A/D interrupt
Internal interrupt (Timer1, Timer0)
External interrupts: PORTA - D (Falling edge)
Oscillator: (OTP option)
Crystal oscillator: 32.768kHz, 400kHz - 8MHz
Ceramic resonator: 400k - 8MHz
External ROSC RC oscillator: 400k - 8MHz
Internal ROSC RC oscillator: 4MHz
External clock: 30k - 8MHz
Instruction cycle time:
4/32.768kHz (≈ 122µs) for 32.768kHz
4/8MHz (= 0.5µs) for 8MHz at VDD = 5.0V
4 channels 8-bit resolution A/D converter
2 channels 10-bit PWM output
Warm-up timer for power on reset
Low voltage reset function (LVR)
Internal reliable reset circuit
Built-in watchdog timer
Two low power operation modes: HALT and STOP
OTP type/Code protection
20-pin DIP/SOP package
General Description
The SH69P42 is an advanced CMOS 4-bit microcontroller. It provides the following standard features: 3K words of OTP ROM,
192 nibbles of RAM, 8-bit timer/counter, 8-bit A/D converter, 10-bit high speed PWM output, on-chip oscillator clock circuitry,
on-chip watchdog timer, low voltage reset function and support power saving modes to reduce power consumption.
Pin Configuration
PORTE.2
PORTE.3
PORTD.2
PORTD.3/PWM1
PORTC.2/PWM0
PORTC.3/T0
RESET /VPP
GND
PORTA.0/AN0/SDA
PORTA.1/AN1
1
2
3
4
5
6
7
8
9
10
20 PORTE.1
19 PORTE.0
18 PORTD.1
17 PORTD.0
16 PORTC.1/VREF
15 OSCO/PORTC.0
14 OSCI/SCK
13 VDD
12 PORTB.3/AN7
11 PORTB.2/AN6
1 V2.1
1 page  
SH69P42
Functional Description
1. CPU
The CPU contains the following functional blocks: Program
Counter (PC), Arithmetic Logic Unit (ALU), Carry Flag (CY),
Accumulator, Table Branch Register, Data Pointer (INX,
DPH, DPM, and DPL) and Stacks.
1.1. PC
The PC is used for ROM addressing consisting of 12-bits:
www.DataSheePt4aUg.ceomRegister (PC11), and Ripple Carry Counter (PC10,
PC9, PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC1, PC0).
The program counter is loaded with data corresponding to
each instruction. The unconditional jump instruction (JMP)
can be set at 1-bit page register for higher than 2K.
The program counter cans only 4K program ROM address.
(Refer to the ROM description).
1.2. ALU and CY
The ALU performs arithmetic and logic operations. The ALU
provides the following functions:
Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI, SBI)
Decimal adjustments for addition/subtraction (DAA, DAS)
Logic operations (AND, EOR, OR, ANDIM, EORIM, ORIM)
Decisions (BA0, BA1, BA2, BA3, BAZ, BC, BNZ, BNC)
Logic Shift (SHR)
The Carry Flag (CY) holds the ALU overflow that the
arithmetic operation generates. During an interrupt service
or call instruction, the carry flag is pushed into the stack and
recovered from the stack by the RTNI instruction. It is
unaffected by the RTNW instruction.
1.3. Accumulator (AC)
The accumulator is a 4-bit register holding the results of the
arithmetic logic unit. In conjunction with the ALU, data is
transferred between the accumulator and system register,
or data memory can be performed.
1.4. Table Branch Register (TBR)
Table Data can be stored in program memory and can be
referenced by using Table Branch (TJMP) and Return
Constant (RTNW) instructions. The Table Branch Register
(TBR) and Accumulator (AC) is placed by an offset address
in program ROM. TJMP instruction branch into address
((PC11 - PC8) X (28) + (TBR, AC)). The address is
determined by RTNW to return look-up value into (TBR,
AC). ROM code bit7 - bit4 is placed into TBR and bit3 - bit0
into AC.
1.5. Data Pointer
The Data Pointer can indirectly address data memory.
Pointer address is located in register DPH (3-bits), DPM
(3-bits) and DPL (4-bits). The addressing range can have
3FFH locations. Pseudo index address (INX) is used to
read or write Data memory, then RAM address bit9 - bit0
comes from DPH, DPM and DPL.
1.6. Stack
The stack is a group of registers used to save the contents
of CY & PC (11-0) sequentially with each subroutine call or
interrupt. The MSB is saved for CY and it is organized into
13 bits X 8 levels. The stack is operated on a first-in,
last-out basis and returned sequentially to the PC with the
return instructions (RTNI/RTNW).
Note:
The stack nesting includes both subroutine calls and
interrupts requests. The maximum allowed for subroutine
calls and interrupts are 8 levels. If the number of calls and
interrupt requests exceeds 8, then the bottom of stack will
be shifted out, that program execution may enter an
abnormal state.
2. RAM
Built-in RAM contains of general-purpose data memory and system register.
2.1. RAM Addressing
Data memory and system register can be accessed in one instruction by direct addressing. The following is the memory
allocation map:
$000 - $02F: System register and I/O
$030 - $0BF: Data memory (144 X 4 bits)
2.2. Data Memory
Data memory is organized as 144 X 4 bits ($030 - $0BF). Because of its static nature, the RAM can keep data after the CPU
enters STOP or HALT.
5
5 Page 
SH69P42
5. System Clock and Oscillator
SH69P42 has one clock source. Oscillator is determined by OTP option. The oscillator generates the basic clock pulses that
provide the system clock to supply CPU and on-chip peripherals.
System clock = fOSC/4.
5.1. Instruction Cycle Time
(a) 4/32.768kHz (≈ 122.1µs) for 32.768kHz oscillator.
(b) 4/8MHz (= 0.5µs) for 8MHz oscillator.
5.2. Oscillator Type
www.DataShee(t4aU) C.croymstal oscillator: 32.768kHz or 400kHz - 8MHz
OSCI
C1
Crystal
OSCO
C2
(b) Ceramic resonator: 400kHz - 8MHz
OSCI
OSCO
C1
Ceramic
C2
(c) RC oscillator: 400kHz - 8MHz
OSCI
ROSC
VDD
1000pF
OSCI
External ROSC RC
(d) External input clock: 30kHz - 8MHz
Internal ROSC RC (fOSC = 4MHz ± 2MHz)
OSCI
External clock source
Note:
If selected RC oscillator or external input clock, OSCO pin is shared with I/O port (PORTC.0).
11
11 Page | ||
| Páginas | Total 37 Páginas | |
| PDF Descargar | [ Datasheet SH69P42.PDF ] | |
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