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79RC32351 데이터시트 PDF




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기능 IDT Interprise Integrated Communications Processor
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79RC32351 데이터시트, 핀배열, 회로
IDTTM InterpriseTM Integrated
Communications Processor
79RC32351
Features List
RC32300 32-bit Microprocessor
– Enhanced MIPS-II ISA
– Enhanced MIPS-IV cache prefetch instruction
– DSP Instructions
– MMU with 16-entry TLB
– 8kB Instruction cache, 2-way set associative
www.DataSheet4U.c2okmB Data cache, 2-way set associative
– Per line cache locking
– Write-through and write-back cache management
– Debug interface through the EJTAG port
– Big or little endian support
Interrupt Controller
– Allows status of each interrupt to be read and masked
UARTs
– Two 16550 Compatible UARTs
– Baud rate support up to 1.5 Mb/s
Counter/Timers
– Three general purpose 32-bit counter/timers
General Purpose I/O Pins (GPIOP)
– 32 individually programmable pins:
each pin programmable as input, output, or alternate function,
input can be an interrupt or NMI source,
input can also be active high or active low
– 4 additional, auxiliary GPIO pins can be configured as input or
output
SDRAM Controller
– 2 memory banks, non-interleaved, 512 MB total
– 32-bit wide data path
– Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips
– SODIMM support
– Stays on page between transfers
– Automatic refresh generation
Peripheral Device Controller
– 26-bit address bus
– 32-bit data bus with variable width support of 8-,16-, or 32-bits
– 8-bit boot ROM support
– 6 banks available, up to 64MB per bank
– Supports Flash ROM, PROM, SRAM, dual-port memory, and
peripheral devices
– Supports external wait-state generation, Intel or Motorola style
– Write protect capability
– Direct control of optional external data transceivers
System Integrity
– Programmable system watchdog timer resets system on time-
out
– Programmable bus transaction times memory and peripheral
transactions and generates a warm reset on time-out
DMA
– 14 DMA channels
– Services on-chip and external peripherals
– Supports memory-to-memory, memory-to-I/O, and I/O-to-I/O
transfers
– Supports flexible descriptor based operation and chaining via
linked lists of records (scatter / gather capability)
– Supports unaligned transfers
Block Diagram
RC32300
CPU Core
ICE EJTAG MMU
D. Cache I. Cache
Interrupt
Controller
:
:
3 Counter
Timers
Watchdog
Timer
10/100
Ethernet
Interface
USB
Interface
16 Channel
DMA
Controller
Arbiter
Ext. Bus
Master
SDRAM &
Device
Controller
2 UARTS
(16550)
GPIO
Interface
ATM
Interface
Memory &
Peripheral Bus
Ch. 1 Ch. 2
Serial Channels
GPIO Pins
Utopia 1 / 2
© 2002 Integrated Device Technology, Inc.
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
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May 25, 2004
DSC 6053




79RC32351 pdf, 반도체, 판매, 대치품
IDT 79RC32351
Thermal Considerations
The RC32351 consumes less than 1.5 W peak power and is guaran-
teed in an ambient temperature range of 0° to +70° C (commercial).
Revision History
January 7, 2002: Initial publication.
May 20, 2002: Added values (in place of TBD) to Table 18, Power
Consumption.
September 19, 2002: Added COLDRSTN Trise1 parameter to Table
5, Reset and System AC Timing Characteristics.
December 6, 2002: In Features section, changed UART speed from
www.Data1S1h5eeKtb4/Us.tcoo1m.5 Mb/s.
December 17, 2002: Added VOH parameter to Table 16, DC Elec-
trical Characteristics.
May 25, 2004: In Table 7, signals MIIRXCLK and MIITXCLK, the Min
and Max values for 10 Mbps Thigh1/Tlow1 were changed to 140 and
260 respectively and the Min and Max values for 100 Mbps Thigh1/
Tlow1 were changed to 14.0 and 26.0 respectively.
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79RC32351 전자부품, 판매, 대치품
IDT 79RC32351
Name
GPIOP[5]
GPIOP[6]
GPIOP[7]
GPIOP[8]
GPIOP[9]
www.DataSheet4U.com
GPIOP[10]
GPIOP[11]
GPIOP[12]
GPIOP[13]
GPIOP[14]
GPIOP[15]
GPIOP[16]
GPIOP[17]
GPIOP[18]
GPIOP[19]
GPIOP[20]
GPIOP[21]
GPIOP[22]
GPIOP[23]
Type I/O Type
Description
I/O Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.
with STI Alternate function: UART channel 0 data set ready, U0DSRN.
I/O Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.
with STI Alternate function: UART channel 0 request to send, U0RTSN.
I/O Low Drive General Purpose I/O.
with STI This pin can be configured as a general purpose I/O pin.
Alternate function: UART channel 0 clear to send, U0CTSN.
I/O Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.
with STI 1st Alternate function: UART channel 1 serial output, U1SOUTP.
2nd Alternate function: Active DMA channel code, DMAP[3].
I/O Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.
with STI 1st Alternate function: UART channel 1 serial input, U1SINP.
2nd Alternate function: Active DMA channel code, DMAP[2].
I/O Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.
with STI 1st Alternate function: UART channel 1 data terminal ready, U1DTRN.
2nd Alternate function: ICE PC trace status, EJTAG_PCST[0].
I/O Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.
with STI 1st Alternate function: UART channel 1 data set ready, U1DSRN.
2nd Alternate function: ICE PC trace status, EJTAG_PCST[1].
I/O Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.
with STI 1st Alternate function: UART channel 1 request to send, U1RTSN.
2nd Alternate function: ICE PC trace status, EJTAG_PCST[2].
I/O Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.
with STI 1st Alternate function: UART channel 1 clear to send, U1CTSN.
2nd Alternate function: ICE PC trace clock, EJTAG_DCLK.
I/O Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.
with STI
I/O Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.
with STI
I/O High Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function: Memory and peripheral bus chip select, CSN[4].
I/O High Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function: Memory and peripheral bus chip select, CSN[5].
I/O Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.
with STI Alternate function: External DMA device request, DMAREQN.
I/O Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.
with STI Alternate function: External DMA device done, DMADONEN.
I/O Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.
with STI Alternate function: USB start of frame, USBSOF.
I/O Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.
with STI Alternate function: SDRAM clock enable CKENP.
I/O Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.
with STI Alternate function: ATM transmit PHY address, TXADDR[0].
I/O Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin.
with STI 1st Alternate function: ATM transmit PHY address, TXADDR[1].
2nd Alternate function: Active DMA channel code, DMAP[0].
Table 1 Pin Descriptions (Part 3 of 7)
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