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W3DG72127V-D2 데이터시트 PDF




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부품번호 W3DG72127V-D2 기능
기능 SDRAM UNBUFFERED
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W3DG72127V-D2 데이터시트, 핀배열, 회로
White Electronic Designs
W3DG72127V-D2
1GB - 128Mx72 SDRAM REGISTERED and SPD, w/PLL
FEATURES
Clock speeds of 100MHz and 133MHz
Burst Mode Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the positive
edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full Page
3.3V ± 0.3V Power Supply
168 Pin DIMM JEDEC
DESCRIPTION
The W3DG72127V is a 128Mx72 synchronous DRAM
module which consists of eighteen 128Mx4 SDRAM
components in TSOP II package, two 18 bit drive ICs
for input control signal and one 2K EEPROM in an 8 pin
TSSOP package for Serial Presence Detect which are
mounted on a 168 Pin DIMM multilayer FR4 Substrate.
* This product is subject to change without notice.
www.DataSheet4U.com
Pin ConfigurATIONs (FRONT SIDE/BACK SIDE)
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
1 VSS 29 DQM1 57 DQ18 85 VSS 113 DQM5 141 DQ50
2 DQ0 30 CS0# 58 DQ19 86 DQ32 114 *CS1# 142 DQ51
3 DQ1 31 DNU 59 VCC 87 DQ33 115 RAS# 143 VCC
4 DQ2 32 VSS 60 DQ20 88 DQ34 116 VSS 144 DQ52
5 DQ3 33 A0 61 NC 89 DQ35 117 A1 145 NC
6 VCC 34 A2 62 *VREF 90 VCC 118 A3 146 *VREF
7 DQ4 35 A4 63 *CKE1 91 DQ36 119 A5 147 REGE
8 DQ5 36 A6 64 VSS 92 DQ37 120 A7 148 VSS
9 DQ6 37 A8 65 DQ21 93 DQ38 121 A9 149 DQ53
10 DQ7 38 A10/AP 66 DQ22 94 DQ39 122 BA0 150 DQ54
11 DQ8 39 BA1 67 DQ23 95 DQ40 123 A11 151 DQ55
12 VSS 40 VCC 68 VSS 96 VSS 124 VCC 152 VSS
13 DQ9 41 VCC 69 DQ24 97 DQ41 125 *CLK1 153 DQ56
14 DQ10 42 CLK0 70 DQ25 98 DQ42 126 *A12 154 DQ57
15 DQ11 43 VSS 71 DQ26 99 DQ43 127 VSS 155 DQ58
16 DQ12 44 DNU 72 DQ27 100 DQ44 128 CKE0 156 DQ59
17 DQ13 45 CS2# 73 VCC 101 DQ45 129 *CS3# 157 VCC
18 VCC 46 DQM2 74 DQ28 102 VCC 130 DQM6 158 DQ60
19 DQ14 47 DQM3 75 DQ29 103 DQ46 131 DQM7 159 DQ61
20 DQ15 48 DNU 76 DQ30 104 DQ47 132 *A13 160 DQ62
21 CB0 49 VCC 77 DQ31 105 CB4 133 VCC 161 DQ63
22 CB1 50 NC 78 VSS 106 CB5 134 NC 162 VSS
23 VSS 51 NC 79 CLK2 107 VSS 135 NC 163 *CLK3
24 NC 52 CB2 80 NC 108 NC 136 CB6 164 NC
25 NC 53 CB3 81 NC 109 NC 137 CB7 165 **SA0
26 VCC 54 VSS 82 **SDA 110 VCC 138 VSS 166 **SA1
27 WE# 55 DQ16 83 **SCL 111 CAS# 139 DQ48 167 **SA2
28 DQM0 56 DQ17 84 VCC 112 DQM4 140 DQ49 168 VCC
PIN NAMES
A0 – A12 Address input (Multiplexed)
BA0-1
Select Bank
DQ0-63
Data Input/Output
CB0-7
Check bit (Data-in/data-out)
CLK0
Clock input
CKE0
Clock Enable input
CS0#,CS2# Chip select Input
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE# Write Enable
DQM0-7 DQM
VCC Power Supply (3.3V)
VSS Ground
*VREF
Power supply for reference
REGE
Register Enable
SDA Serial data I/O
SCL Serial clock
SA0-2
Address in EEPROM
DNU Do not use
NC No Connect
* These pins are not used in this module.
** These pins should be NC in the system which
does not support SPD.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 2
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com




W3DG72127V-D2 pdf, 반도체, 판매, 대치품
White Electronic Designs
W3DG72127V-D2
Parameters
Operating Current
(One bank active)
Precharge Standby Current
in Power Down Mode
Precharge Standby Current
in Non-Power Down Mode
Active standby current in
power-down mode
OPERATING CURRENT CHARACTERISTICS
VCC = 3.3V, 0°C TA 70°C
Symbol Conditions
ICC1
ICC2P
ICC2PS
ICC2N
ICC2NS
ICC3P
Burst Length = 1
tRC ≥ tRC(min)
IOL = 0mA
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC =10ns
Input signals are charged one time during 20
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC= ∞
Input signals are stable
CKE ≥ VIL(max), tCC = 10ns
Versions
133/100
3885
395
330
825
275
465
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞
372
www.DAcativtae sStahndebyeint4cuUrre.nctonomn power-
down mode
ICC3N
ICC3NS
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are charged one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
input signals are stable
Operating current (Burst mode)
Io = mA
ICC4
Page burst
4 Banks activated
tCCD = 2CLK
Refresh current
ICC5 tRC ≥ tRC(min)
Self refresh current
ICC6 CKE ≤ 0.2V
Notes: 1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS (VIH/VIL = VCC/VSSQ)
1185
830
3885
6225
411
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Note
1
1
2
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 2
4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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W3DG72127V-D2

SDRAM UNBUFFERED

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